Semiconductor memory device
View Patent ↗An object of the present invention is to provide a technique of reducing the power consumption of an entire low power consumption SRAM LSI circuit employing scaled-down transistors and of increasing the stability of read and write operations on the memory cells by reducing the subthreshold leakage current and the leakage current flowing from the drain electrode to the substrate electrode. Another object of the present invention is to provide a technique of preventing an increase in the number of transistors in a memory cell and thereby preventing an increase in the cell area. Still another object of the present invention is to provide a technique of ensuring stable operation of an SRAM memory cell made up of SOI or FD-SOI transistors having a BOX layer by controlling the potentials of the wells under the BOX layers of the drive transistors.
1. A semiconductor memory device functioning as a static memory cell, said semiconductor memory device comprising:
a plurality of SOI transistors each including a well layer made up of a conductive layer and formed on a semiconductor substrate, a BOX layer made up of an insulation layer and formed on said well layer, a source layer and a drain layer that are formed on said BOX layer, a channel layer sandwiched between said source and drain layers, and a gate electrode formed on said channel layer with a gate insulation layer therebetween;
a pair of drive transistors each made up of one of said plurality of SOI transistors and including a channel of a first conductive type and a source electrode that is connected to a ground line;
a pair of load transistors each made up of one of said plurality of SOI transistors and including a channel of a second conductive type, a source electrode, and a drain electrode, said source electrode being connected to a first power supply line higher in potential than said ground line, said drain electrode being connected to one of said pair of drive transistors; and
a pair of transfer transistors each made up of one of said plurality of SOI transistors and including a channel of said first conductive type, each transfer transistor being connected between a bit line for accessing said memory cell and a storage node for storing information;
wherein a well layer in which one of said pair of drive transistors is formed and a well layer in which one of said pair of transfer transistors is formed are provided on a first common well layer; wherein said pair of load transistors are provided on a second common well layer; and
wherein said first and second common well layers are electrically isolated from each other.
2. The semiconductor memory device as claimed in claim 1 , wherein said pair of load transistors are formed in different well layers.