Shared upper level cache architecture

1. An apparatus to implement a shared cache architecture, the apparatus comprising:

a multi-core processor comprising a first subset of processor cores and a second subset of processor cores;

a first shared cache memory coupled to the first subset of processor cores and configured to be accessible to the first subset of processor cores;

a second shared cache memory coupled to the second set of processor cores and configured to be accessible to the second subset of processor cores; and

a module coupled to the first shared cache memory and the second shared cache memory and configured to;

access data stored in a first subset of one or more memory locations in the first shared cache memory wherein the data is to be accessed by one or more of the first subset of processor cores and one or more of the second subset of processor cores;

mirror the data;

store the mirrored data in a second subset of one or more memory locations in the second shared cache memory; and

update the mirrored data responsive to modification of the mirrored data by any of the first subset of processor cores and/or the second subset of processor cores,

wherein the first subset of processor cores includes different processor cores than the second subset of processor cores.

2. The apparatus of claim 1 , wherein the multi-core processor includes a third subset of processor cores, the apparatus further comprising:

a third shared cache memory coupled to the third subset of processor cores and configured to be accessible to the third subset of processor cores,

wherein the third subset of processor cores includes different processor cores than the first subset of processor cores and the second subset of processor cores.

3. The apparatus of claim 1 , wherein the first shared cache memory comprises cache memory adjacent to the first subset of processor cores, and

wherein the second shared cache memory comprises cache memory adjacent to the second subset of processor cores.

4. The apparatus of claim 1 , wherein the first shared cache memory comprises cache memory having closer physical proximity to the first subset of processor cores than to the second subset of processor cores.

5. The apparatus of claim 1 , further comprising:

main memory coupled to the first and second subsets of processor cores and configured to be accessible to both the first subset of processor cores and the second subset of processor cores.

6. The apparatus of claim 1 , further comprising:

a first plurality of low level cache memories, each low level cache memory of the first plurality of low level cache memories coupled to and associated with a different processor core of the first subset of processor cores.

7. The apparatus of claim 6 , further comprising:

a second plurality of low level cache memories, each low level cache memory of the second plurality of low level cache memories coupled to and associated with a different processor core of the second subset of the processor cores.

8. The apparatus of claim 1 , wherein the multi-core processor, the first shared cache memory and the second shared cache memory are formed on a semiconductor die.

9. The apparatus of claim 1 , wherein the first shared cache memory is further configured to not be accessible to the second subset of processor cores and the second shared cache memory is further configured to not be accessible to the first subset of processor cores.

10. A method to share cache memory by processor cores of a multi-core processor, the method comprising:

accessing a first shared cache memory by one or more processor cores of a first plurality of processor cores;

accessing a second shared cache memory by one or more processor cores of a second plurality of processor cores;

accessing data from the first shared cache memory by a module;

mirroring the data by the module;

storing the mirrored data in the second shared cache memory by the module based at least in part in response to the data being written to the first shared cache memory by one or more processor cores of the first plurality of processor cores; and

accessing the mirrored data by one or more processor cores of the second plurality of processor cores,

wherein the first plurality of processor cores includes different processor cores than the second plurality of processor cores.

11. The method of claim 10 , further comprising:

accessing a third shared cache memory by one or more processor cores of a third plurality of processor cores,

wherein the third plurality of processor cores includes different processor cores than the first plurality of processor cores and the second plurality of processor cores.

12. The method of claim 10 , further comprising:

accessing a first local cache memory by a first processor core of the first plurality of processor cores; and

accessing a second local cache memory by a second processor core of the first plurality of processor cores.

13. A shared cache system, the system comprising:

a multi-core processor comprising a first subset of processor cores and a second subset of processor cores;

a first shared cache memory coupled to the first subset of processor cores and configured to be accessible to the first subset of processor cores;

a second shared cache memory coupled to the second set of processor cores and configured to be accessible to the second subset of processor cores; and

a module coupled to the first shared cache memory and the second shared cache memory and configured to:

access data from the first shared cache memory;

provide duplicate copies of the data to both the first shared cache memory and the second shared cache memory; and

update the copied data in the first shared cache memory and the second shared cache memory responsive to modification of the data by any of the first subset of processor cores or the second subset of processor cores.

14. The system of claim 13 , wherein the multi-core processor includes a third subset of processor cores, the system further comprising:

a third shared cache memory coupled to the third subset of processor cores and configured to be accessible to the third subset of processor cores.

15. The system of claim 13 , wherein the first shared cache memory comprises cache memory adjacent to the first subset of processor cores, and

wherein the second shared cache memory comprises cache memory adjacent to the second subset of processor cores.

16. The system of claim 13 , wherein the first shared cache memory comprises cache memory having closer physical proximity to the first subset of processor cores than to the second subset of processor cores.

17. The system of claim 13 , wherein the multi-core processor, the plurality of local cache memories, the first shared cache memory and the second shared cache memory are formed on a semiconductor die.

18. The system of claim 13 , wherein the first shared cache memory is further configured to not be accessible to the second subset of processor cores and the second shared cache memory is further configured to not be accessible to the first subset of processor cores.

19. An article, comprising:

a non-transitory computer program product including instructions stored therein that, if executed, result in:

accessing a first shared cache memory by one or more processor cores of a first plurality of processor cores;

accessing a second shared cache memory by one or more processor cores of a second plurality of processor cores;

accessing data from the first shared cache memory by a module;

mirroring the data by the module; and

storing the mirrored data in the second shared cache memory by the module based at least in part in response to the data being written to the first shared cache memory by the first plurality of processor cores,

wherein the first plurality of processor cores includes different processor cores than the second plurality of processor cores.

20. The article of claim 19 , wherein the non-transitory computer program product further includes instructions stored therein that, if executed, result in:

accessing a third shared cache memory by one or more processor cores of a third plurality of processor cores, wherein the third plurality of processor cores includes different processor cores than the first plurality of processor cores and the second plurality of processor cores.

21. The article of claim 20 , wherein the non-transitory computer program product further includes instructions stored therein that, if executed, result in storing the mirrored data in the third shared cache memory.