Power line preconditioner for improved LED intensity control
View Patent ↗A switched preconditioner circuit is provided at the power input end of a light source to effectively drop the voltage of the light source to zero volts whenever the light source is required to be in an OFF state thereby eliminating the problem of unwanted current through the light source. The preconditioner circuit may include a terminal connected to a first power potential, a terminal connected to a power node at the power input end of the light source, and an input to receive a preconditioner control signal to place the preconditioner circuit in one of an ON state and an OFF state. The preconditioner circuit supplies the voltage to the power node in its ON state and effectively eliminates the voltage to the power node in its OFF state. The preconditioner circuit also may include a bleed path connected between the power node and a second or ground potential to shunt all power supplied to the power node when the preconditioner circuit input receives a signal to place the preconditioner circuit in the OFF state.
1. A system comprising:
a first power potential configured to supply a voltage;
a second power potential;
a power supply circuit configured for connection to a light source and including a power supply side and a power return side;
a power node connected to the power supply side;
a current switch connected between the power return side and the second potential, the current switch including an input configured to receive a current switch control signal to place the switch in one of an ON state and an OFF state allowing current to flow through the current switch in the ON state;
a preconditioner circuit connected to the first power potential and the power node, the preconditioner circuit including an input configured to receive a preconditioner control signal to place the preconditioner circuit in one of an ON state and an OFF state, wherein the preconditioner circuit is configured to supply voltage to the power node in its ON state and effectively eliminate the voltage to the power node in its OFF state; and
a bleed path between the power node and the second potential and configured to shunt all power supplied to the power node when the preconditioner circuit input receives a signal to place the preconditioner circuit in the OFF state.
2. The system of claim 1 wherein the preconditioner circuit includes a preconditioner connected between the first potential and the power node.
3. The system of claim 2 wherein the preconditioner is a field effect transistor having a gate to receive the preconditioner control signal.
4. The system of claim 2 wherein the bleed path has a first impedance and the current switch has a second impendence in the OFF state that is greater than the first impedance.
5. The system of claim 1 wherein the preconditioner control signal includes a pulse having a longer duration than a corresponding pulse of the current control single and is timed to pulse high before the current control signal pulses high and is timed to pulse low after the current control signal pulses low.
6. The system of claim 1 further comprising a processing device to generate the current switch control signal and the preconditioner control signal.
7. The system of claim 6 , wherein the processing device is a software-programmed processor, a firmware-programmed processor, or a programmable logic device (PLD).
8. The system of claim 7 , wherein the programmable logic device (PLD) comprises a programmable array logic (PAL) device.
9. The system of claim 7 , wherein the programmable logic device (PLD) comprises a programmable logic array (PLA) device.
10. The system of claim 1 wherein the light source is a light emitting diode.
11. The system of claim 1 wherein the light source is an array of light emitting diodes.
12. The system of claim 1 wherein the light source is a light emitting diode of a display device.
13. A preconditioner circuit for use in a lighting circuit including a first power potential supplying a voltage, a second power potential, a light source have a power supply side and a power return side, a power node connected to the power supply side of the light source, and a current switch connected between the power return side of the light source and the second potential, the current switch including an input to receive a current switch control signal to place the switch in one of an ON state and an OFF state allowing current to flow through the current switch in the ON state, the preconditioner circuit comprising:
a terminal connected to the first power potential;
a terminal connected to the power node,
an input configured to receive a preconditioner control signal and to place the preconditioner circuit in one of an ON state and an OFF state, wherein the preconditioner circuit is configured to supply voltage to the power node in its ON state and eliminate the voltage to the power node in its OFF state; and
a bleed path between the power node and the second potential and configured to shunt all power supplied to the power node when the preconditioner circuit input receives a signal to place the preconditioner circuit in the OFF state.
14. The circuit of claim 13 wherein the bleed path has a first impedance that is less than an impedance of the current switch when the current switch is in the OFF state.
15. The circuit of claim 13 wherein the preconditioner control signal includes a pulse having a longer duration than a corresponding pulse of the current control single and is timed to pulse high before the current control signal pulses high and is timed to pulse low after the current control signal pulses low.
16. The circuit of claim 13 wherein the precondition control signal is received from a processing device.
17. The circuit of claim 16 , wherein the processing device is a software-programmed processor, a firmware-programmed processor, or a programmable logic device (PLD).
18. The circuit of claim 17 , wherein the programmable logic device (PLD) comprises a programmable array logic (PAL) device.
19. The circuit of claim 17 , wherein the programmable logic device (PLD) comprises a programmable logic array (PLA) device.