Memory system with point-to-point request interconnect
A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports. The request ports are coupled, via point-to-point connections, to from one to N memory devices, each of which includes N independently addressable memory blocks. All of the external request ports are connected to respective external request ports on the memory device or devices used in a given configuration. The number of request ports per memory device and the data width of each memory device changes with the number of memory devices such that the ratio of the request-access granularity to the data granularity remains constant irrespective of the number of memory devices.
1. An integrated circuit memory device comprising:
a request interface supporting an operational mode and a loop-back mode, wherein the request interface receives and decodes memory requests in the operational mode and receives test patterns in the loop-back mode;
a bidirectional interface supporting the operational mode and the loop-back mode, wherein the bidirectional interface receives signals in the operational mode and transmits the test patterns in the loop-back mode; and
loop-back test circuitry to selectively couple the request interface to the bidirectional interface, in the loop-back mode, to convey the test patterns from the request interface to the bidirectional interface.
2. The memory device of claim 1 , further comprising a memory block coupled to the bidirectional interface to store data, wherein the bidirectional interface is a data interface, and wherein the signals received in the operational mode represent the data.
3. The memory device of claim 1 , wherein the data and request interfaces operate at a same symbol rate.
4. The memory device of claim 1 , further comprising a memory block to store data, wherein the bidirectional interface is a second request interface supporting the operational mode and the loop-back mode, and wherein the signals received in the operational mode are second memory requests.
5. The memory device of claim 1 , wherein the request interface receives the test patterns at a first symbol rate, the memory device further comprising a command interface to receive commands at a second symbol rate lower than the first symbol rate.
6. The memory device of claim 5 , further comprising a command decoder coupled to the command interface, the command decoder to receive a command directing the memory device to enter the loop-back mode.
7. The memory device of claim 1 , wherein the request interface is bidirectional.
8. The memory device of claim 1 , wherein the request and bidirectional interfaces further support a third mode in which the request interface and the bidirectional interface transmit second test patterns.
9. The memory device of claim 8 , further comprising a memory block and an address generator coupled to the memory block to generate addresses in the third mode.
10. The memory device of claim 1 , further comprising a memory block and a dummy-address generator coupled to the memory block to generate dummy addresses in the loop-back mode.
11. A memory controller comprising:
a request interface supporting an operational mode and a loop-back mode, wherein the request interface transmits memory requests in the operational mode and transmits test patterns in the loop-back mode; and
a bidirectional interface supporting the operational mode and the loop-back mode, wherein the bidirectional interface transmits signals in the operational mode and receives the test patterns in the loop-back mode.
12. The memory controller of claim 11 , wherein the bidirectional interface is a data interface, the transmitted signals are write-data signals, and the bidirectional interface receives read-data signals in the operational mode.
13. The memory controller of claim 11 , wherein the bidirectional interface is a second request interface that transmits second memory requests in the operational mode.
14. A method performed by a memory device having a request interface, a data interface, and a memory, the method comprising:
in a loop-back mode, receiving test signals via the request interface, conveying the test signals to the data interface, and transmitting the test signals from the data interface;
storing data in the memory; and
in an operational mode, receiving request signals representing read requests on the request interface, reading the data from the memory responsive to the read requests, and transmitting the data over the data interface.
15. The method of claim 14 , further comprising generating second test signals on the memory device and conveying the second test signals from the memory device over the request interface or the data interface.
16. The method of claim 15 , further comprising generating address signals on the memory device and addressing the memory using the generated address signals while conveying the second test signals from the memory device.