Flash memory device and manufacturing method of the same
View Patent ↗A flash memory device may include a device isolation layer and an active area formed over a semiconductor substrate, a memory gate formed over the active area, and a control gate formed over the semiconductor substrate including the memory gate, wherein the active area, where a source contact is to be formed, has the same interval spacing as a bit line, and a common source line area, where the source contact is to be formed, has an impurity area connecting neighboring active areas.
1. An apparatus comprising:
a device isolation layer and an active area formed over a semiconductor substrate;
a memory gate formed over the active area; and
a control gate formed over the semiconductor substrate including the memory gate, wherein the active area, where a source contact is to be formed, has the same interval spacing as a bit line, and a common source line area, where the source contact is to be formed, has an impurity area connecting neighboring active areas.
2. The apparatus of claim 1 , wherein the impurity area is formed below the device isolation layer.
3. The apparatus of claim 1 , wherein the impurity area connects at least three active areas.
4. The apparatus of claim 1 , wherein the source contact is aligned with a drain contact.
5. The apparatus of claim 1 , wherein the control gate is straight and parallel with a neighboring control gate.
6. The apparatus of claim 1 , wherein the device isolation layer and the active area formed over a semiconductor substrate, the memory gate formed over the active area, and the control gate form part of a flash memory device.
7. The apparatus of claim 4 , wherein the drain contact is formed on the bit line.
8. The apparatus of claim 5 , wherein the control gate crosses the active area.
9. A method comprising:
forming a trench on a semiconductor substrate;
forming an impurity area in the trench formed between areas where a source contact is to be formed;
forming an active area by forming a device isolation layer by burying insulating material into the trench; and
forming a memory gate and a control gate over the device isolation layer, wherein the active area where a source contact is to be formed has the same spacing interval as a bit line, and the impurity area connects the neighboring active areas where the source contact is formed.
10. The method of claim 9 , wherein the impurity area is formed below the device isolation layer.
11. The method of claim 9 , wherein the impurity area connects at least three active areas.
12. The method of claim 9 , wherein the source contact is aligned with a drain contact.
13. The method of claim 9 , wherein the wherein the control gate is straight and parallel with a neighboring control gate.
14. The method of claim 9 , wherein the control gate crosses the active area.
15. The method of claim 9 , wherein the forming the impurity area in the trench comprises:
opening the trench between the areas where the source contact is to be formed by forming a photoresist pattern over the semiconductor substrate including the trench; and
forming the impurity area at the side walls and the bottom surface of the trench by performing a first ion implantation process and a second ion implantation process on the semiconductor substrate.
16. The method of claim 12 , wherein the drain contact formed on the bit line.
17. The method of claim 15 , wherein the first ion implantation process and the second ion implantation process are performed using V family element at an angle of 0 to 30°.
18. The method of claim 15 , wherein the first ion implantation process and the second ion implantation process are performed at an energy of 1 KeV to 100 KeV.
19. The method of claim 15 , wherein the first ion implantation process and the second ion implantation process are performed with ion doses ranging from 1×10 13 to 1×10 16 ion/cm 2 .
20. The method of claim 15 , wherein after the first ion implantation process is performed, the semiconductor substrate is rotated, and the second ion implantation process is performed.