Layout patterns for deep well region to facilitate routing body-bias voltage
View Patent ↗Layout patterns for the deep well region to facilitate routing the body-bias voltage in a semiconductor device are provided and described. The layout patterns include a diagonal sub-surface mesh structure, an axial sub-surface mesh structure, a diagonal sub-surface strip structure, and an axial sub-surface strip structure. A particular layout pattern is selected for an area of the semiconductor device according to several factors.
1. A semiconductor device comprising:
a plurality of well regions of a first conductivity;
a sub-surface structure of said first conductivity coupled to said well regions, wherein said sub-surface structure comprises a portion having a depth greater than depth of said well regions; and
at least one contact coupled to said sub-surface structure, wherein said contact is operable to receive a voltage to enable said sub-surface structure to route said voltage to said well regions.
2. The semiconductor device of claim 1 , wherein said voltage comprises a body-bias voltage.
3. The semiconductor device of claim 1 , wherein said well regions have an N-type doping.
4. The semiconductor device of claim 1 , wherein said sub-surface structure has an N-type doping.
5. The semiconductor device of claim 1 , wherein said sub-surface structure comprises a diagonal sub-surface mesh structure.
6. The semiconductor device of claim 1 , wherein said sub-surface structure comprises an axial sub-surface mesh structure.
7. The semiconductor device of claim 1 , wherein said sub-surface structure comprises a diagonal sub-surface strip structure.
8. The semiconductor device of claim 1 , wherein said sub-surface structure comprises an axial sub-surface strip structure.
9. A semiconductor device comprising:
a plurality of well regions of a first conductivity;
a plurality of sub-surface structures of said first conductivity, wherein each sub-surface structure is coupled to a subset of said well regions, and wherein each sub-surface structure comprises a portion having a depth greater than depth of said well regions; and
a plurality of contacts, wherein each contact is coupled to one of said sub-surface structures, and wherein each contact is operable to receive a voltage to enable said sub-surface structures to route said voltage to said well regions.
10. The semiconductor device of claim 9 , wherein said voltage comprises a body-bias voltage.
11. The semiconductor device of claim 9 , wherein said well regions have an N-type doping.
12. The semiconductor device of claim 9 , wherein said sub-surface structures have an N-type doping.
13. The semiconductor device of claim 9 , wherein said sub-surface structures comprise at least one diagonal sub-surface mesh structure.
14. The semiconductor device of claim 9 , wherein said sub-surface structures comprise at least one axial sub-surface mesh structure.
15. The semiconductor device of claim 9 , wherein said sub-surface structures comprise at least one diagonal sub-surface strip structure.
16. The semiconductor device of claim 9 , wherein said sub-surface structures comprise at least one axial sub-surface strip structure.
17. A semiconductor device comprising:
a plurality of well regions of a first conductivity;
a plurality of regions of a second conductivity, wherein said regions and said well regions are arranged in an alternating pattern;
a plurality of sub-surface structures of said first conductivity, wherein each sub-surface structure is coupled to a subset of said well regions without isolating any regions of said second conductivity, and wherein each sub-surface structure comprises a portion having a depth greater than depth of said well regions; and
a plurality of contacts, wherein each contact is coupled to one of said sub-surface structures, and wherein each contact is operable to receive a voltage to enable said sub-surface structures to route said voltage to said well regions.
18. The semiconductor device of claim 17 , wherein said voltage comprises a body-bias voltage.
19. The semiconductor device of claim 17 , wherein said well regions of said first conductivity have an N-type doping, and wherein said regions of said second conductivity have a P-type doping.
20. The semiconductor device of claim 17 , wherein said sub-surface structures have an N-type doping.
21. The semiconductor device of claim 17 , wherein said sub-surface structures comprise at least one diagonal sub-surface mesh structure.
22. The semiconductor device of claim 17 , wherein said sub-surface structures comprise at least one axial sub-surface mesh structure.
23. The semiconductor device of claim 17 , wherein said sub-surface structures comprise at least one diagonal sub-surface strip structure.
24. The semiconductor device of claim 17 , wherein said sub-surface structures comprise at least one axial sub-surface strip structure.