Semiconductor device
View Patent ↗A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.
1. A semiconductor device comprising:
a logic circuit including a plurality of metal insulator semiconductor (MIS) transistors and a memory array including a plurality of static memory cells;
a first switch connected between an operating voltage supply point of the logic circuit and a first power line which supplies a first voltage;
a voltage control circuit connected between an operating voltage supply point of the memory array and a second power line which supplies a second voltage; and
a control circuit which controls the first switch.
2. A semiconductor device according to claim 1 ,
wherein the voltage control circuit controls power supply voltage of the memory array.
3. A semiconductor device according to claim 2 ,
wherein the second voltage is higher than the first voltage.
4. A semiconductor device according to claim 2 ,
wherein the control circuit and the voltage control circuit are controlled by a standby signal.
5. A semiconductor device according to claim 1 ,
wherein the voltage control circuit includes a voltage dropping circuit and a second switch, and
wherein the second switch controls the power supply voltage of the memory array by switching a third voltage outputted from the voltage dropping circuit and the second voltage.
6. A semiconductor device according to claim 5 ,
wherein the third voltage is higher than the first voltage and lower than the second voltage.
7. A semiconductor device according to claim 6 ,
wherein each said static memory cell includes a plurality of N channel MIS transistors and a plurality of P channel MIS transistors, and
wherein the semiconductor device includes a substrate bias controller which controls substrate voltages of the plurality of N channel MIS transistors and the plurality of P channel MIS transistors.
8. A semiconductor device comprising:
a logic circuit including a plurality of metal insulator semiconductor (MIS) transistors and a memory array including a plurality of static memory cells;
a first switch connected between an operating voltage supply point of the logic circuit and a first power line which supplies a first voltage;
a voltage control circuit connected between an operating voltage supply point of the memory array and the first power line; and
a control circuit which controls the first switch.
9. A semiconductor device according to claim 8 ,
wherein the voltage control circuit controls power supply voltage of the memory array.
10. A semiconductor device according to claim 9 ,
wherein the logic circuit and the memory array are coupled to a second voltage line which supplies a second voltage, and
the second voltage is higher than the first voltage.
11. A semiconductor device according to claim 9 ,
wherein the control circuit and the voltage control circuit are controlled by a standby signal.
12. A semiconductor device according to claim 8 ,
wherein the voltage control circuit includes a voltage raising circuit and a second switch, and
wherein the second switch controls the power supply voltage of the memory array by switching a voltage outputted from the voltage raising circuit and the first voltage.
13. A semiconductor device according to claim 12 ,
wherein the voltage outputted from the voltage raising circuit is higher than the first voltage and lower than the second voltage.
14. A semiconductor device according to claim 13 ,
wherein each said static memory cell includes a plurality of N channel MIS transistors and a plurality of P channel MIS transistors, and
wherein the semiconductor device includes a substrate bias controller which controls substrate voltages of the plurality of N channel MIS transistors and the plurality of P channel MIS transistors.