Ge imager for short wavelength infrared
A germanium (Ge) short wavelength infrared (SWIR) imager and associated fabrication process are provided. The imager comprises a silicon (Si) substrate with doped wells. An array of pin diodes is formed in a relaxed Ge-containing film overlying the Si substrate, each pin diode having a flip-chip interface. There is a Ge/Si interface, and a doped Ge-containing buffer interposed between the Ge-containing film and the Ge/Si interface. An array of Si CMOS readout circuits is bonded to the flip-chip interfaces. Each readout circuit has a zero volt diode bias interface.
1. A germanium (Ge) short wavelength infrared (SWIR) imager, the imager comprising:
a silicon (Si) substrate with doped wells;
an array of pin diodes formed in a relaxed Ge-containing film overlying the Si substrate, each pin diode having a flip-chip interface;
a Ge/Si interface;
a doped Ge-containing buffer layer interposed between the Ge-containing film and the Ge/Si interface; and,
an array of Si CMOS readout circuits bonded to the flip-chip interfaces, each readout circuit having about a zero volt diode bias interface.
2. The imager of claim 1 wherein the doped Ge-containing buffer layer is transparent to light having a wavelength in the range of about 1100 nanometers (nm) to 1600 nm.
3. The imager of claim 1 wherein the doped Ge-containing buffer layer transmits more than about 75% of incident light.
4. The imager of claim 1 wherein the doped Ge-containing buffer layer has a thickness of less than about 0.25 microns.
5. The imager of claim 1 wherein each diode in the array of pin diodes includes an active region formed with a thickness sufficient to absorb light having a wavelength in the range of about 1100 nm to 1600 nm.
6. The imager of claim 5 wherein each pin diode active region has a thickness in the range of about 1 to 5 microns.
7. The imager of claim 1 wherein each readout circuit in the array of Si CMOS readout circuits includes a diode interface with a bias of less than 0.001 volts.
8. The imager of claim 7 wherein each Si CMOS readout circuit includes an operational amplifier with two inputs and an open circuit gain of greater than about 10,000, where the diode interface is formed across the operational amplifier inputs, forming a diode bias voltage inversely proportional to the operational amplifier open circuit gain.
9. The imager of claim 1 wherein each pin diode includes an isolated Ge intrinsic region with a boundary formed to the level of the doped Ge-containing buffer layer, the boundary made from a material selected from a group including an interlevel dielectric and a doped Ge-containing film.