Semiconductor device and method for manufacturing the same

1. A semiconductor device comprising:

a substrate having a first conductor-type;

a buried layer having a second conductor-type on or over the substrate;

a drain; and

a first guard-ring on one side of the drain, a second guard-ring on one side of the first guard-ring, and a third guard-ring on one side of the second guard-ring, wherein the first guard-ring comprises a first conductor-type well and an impurity region, the impurity region being within the first conductor-type well.

2. The semiconductor device of claim 1 , wherein the second guard-ring comprises a second conductor-type well and an impurity region, the impurity region being in the second conductor-type well.

3. The semiconductor device of claim 1 , wherein a field oxide layer is in a region between the second guard-ring and the first guard-ring.

4. The semiconductor device of claim 1 , wherein the second guard-ring comprises an N-type well having N-type impurities injected therein, and an N-type impurity region within the N-type well.

5. The semiconductor device of claim 1 , wherein a field oxide layer is between the first guard-ring and the drain of the semiconductor device.

6. The semiconductor device of claim 1 , wherein the third guard-ring corresponds to an impurity region having impurities of the second conductor-type therein, and the field oxide layer is on the substrate above an upper side of the third guard-ring.

7. The semiconductor device of claim 6 , wherein the impurities of the second conductor-type comprise N-type impurities.

8. A lateral double diffusion MOSFET (LDMOS), comprising the semiconductor device of claim 1 .

9. The semiconductor device of claim 1 , wherein the third guard-ring comprises a second conductor-type well.

10. The semiconductor device of claim 9 , wherein the second-conductor-type well comprises an N-type well.

11. A semiconductor device comprising:

a substrate having a first conductor-type, an active region and a field region;

a second conductor-type deep well in the substrate;

a first conductor-type body in the deep well;

a gate electrode on or over the active region;

a second conductor-type drain region and a second conductor-type source region in the body and in the deep well;

a first guard well in the second conductor-type deep well and having first conductor-type impurities therein;

a second guard well in the deep well and having second conductor-type impurities therein; and

a third guard well in the deep well and having second conductor-type impurities therein.

12. The semiconductor device of claim 11 , wherein the first guard well is spaced apart from the second drain region at a predetermined distance by a field oxide layer.

13. The semiconductor device of claim 11 , wherein the second guard well is spaced apart from the first guard well at a predetermined distance by a field oxide layer.

14. The semiconductor device of claim 11 , wherein the second guard well comprises a P-type well, and a P + -type impurity region formed in the P-type well.

15. The semiconductor device of claim 11 , wherein a field oxide layer is on the third guard well.

16. The semiconductor device of claim 11 , wherein the second conductor-type deep well comprises an N-type deep well.

17. The semiconductor device of claim 11 , wherein the second guard well further comprises an impurity region.

18. The semiconductor device of claim 17 , wherein the impurity region comprises an N-type impurity region, the N-type impurity region within the second guard well.

19. The semiconductor device of claim 11 , wherein the second conductor-type impurities comprise N-type impurities.

20. A lateral double diffusion MOSFET (LDMOS) comprising the semiconductor device of claim 11 .