IP Library Granted Patent US 8,164,935
Granted Patent B2
US 8,164,935 · App. 12/632,176 · Granted Apr 24, 2012

Memory modules and methods for modifying memory subsystem performance

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Quick Facts
Patent No.
US 8,164,935
App. No.
12/632,176
Granted
Apr 24, 2012
Kind
B2
Abstract

Methods and memory modules adapted for use in computer systems to generate different voltages for core supply (VDD) and input/output supply (VDDQ) inputs to memory components of the computer memory subsystem. The memory module includes a substrate with an edge connector, a memory component, and first and second voltage planes adapted to supply the core supply voltage and the input/output supply voltage to the memory component. The first voltage plane receives a system input voltage from the edge connector, and the second voltage plane is connected to the first voltage plane to receive a second voltage that is either higher or lower than the system input voltage. One of the first and second voltage planes is connected to the memory component to supply the core supply voltage thereto, and the other voltage plane supplies the input/output supply voltage to the memory component.

Claims (30)

1. A memory module adapted for use in a computer system having a system input voltage, the module comprising:

a substrate;

an edge connector on the substrate and comprising at least first and second input pins adapted to receive the system input voltage from the computer system;

electrical connections on the substrate that tie the first and second input pins so that a voltage applied to one of the first and second input pins is also applied to the other of the first and second input pins;

at least one memory component mounted on the substrate and electrically interconnected with the edge connector to receive a core supply voltage and an input/output supply voltage; and

first and second voltage planes defined on the substrate and adapted to supply the core supply voltage and the input/output supply voltage to the memory component, the first voltage plane being connected to the first and second input pins of the edge connector for receiving the system input voltage therefrom, and the second voltage plane being connected through a voltage-altering device to the first voltage plane to receive a second voltage that is either higher or lower than the system input voltage of the first voltage plane, wherein one of the first and second voltage planes is connected to the memory component to supply the core supply voltage thereto and the other of the first and second voltage planes is connected to the memory component to supply the input/output supply voltage thereto.

2. The memory module of claim 1 , wherein the input/output supply voltage is lower than the core supply voltage.

3. The memory module of claim 1 , wherein the second voltage of the second voltage plane is lower than the system input voltage of the first voltage plane.

4. The memory module of claim 3 , wherein the first voltage plane supplies the core supply voltage to the memory component, and the second voltage planes supplies the input/output supply voltage to the memory component.

5. The memory module of claim 4 , wherein the core supply voltage is equal to the system input voltage of the first voltage plane, and the input/output supply voltage is equal to the second voltage of the second voltage plane.

6. The memory module of claim 3 , wherein the voltage-altering device comprises a diode connecting the first and second voltage planes and adapted to reduce the second voltage of the second voltage plane relative to the system input voltage of the first voltage plane.

7. The memory module of claim 3 , wherein the voltage-altering device comprises a linear regulator circuit connecting the first and second voltage planes and adapted to reduce the second voltage of the second voltage plane relative to the system input voltage of the first voltage plane.

8. The memory module of claim 1 , wherein the second voltage of the second voltage plane is higher than the system input voltage of the first voltage plane.

9. The memory module of claim 8 , wherein the first voltage plane supplies the input/output supply voltage to the memory component, and the second voltage planes supplies the core supply voltage to the memory component.

10. The memory module of claim 9 , wherein the input/output supply voltage is equal to the system input voltage of the first voltage plane, and the core supply voltage is equal to the second voltage of the second voltage plane.

11. The memory module of claim 8 , further comprising a boost DC-DC converter between the first and second voltage planes and adapted to boost the second voltage of the second voltage plane relative to the system input voltage of the first voltage plane.

12. The memory module of claim 11 , further comprising a Schottky diode connecting the first and second voltage planes and adapted to limit delays and voltage lags between the first and second voltage planes.

13. A method of supplying two different voltages to at least one core supply input pin and at least one input/output supply input pin of at least one memory component on a substrate of a memory module that receives a system input voltage from a computer system, the method comprising:

configuring the substrate to have a first voltage plane and first and second input pins to which the first voltage plane is connected so that a voltage applied to one of the first and second input pins is also applied to the other of the first and second input pins and to the first voltage plane;

connecting the module to the computer system so that the first voltage plane receives the system input voltage from the computer system through the first and second input pins;

deriving the two different voltages from the system input voltage of the first voltage plane;

delivering a first of the two different voltages to the core supply input pin of the memory component; and

delivering a second of the two different voltages to the input/output supply input pin of the memory component.

14. The method of claim 13 , wherein the second of the two different voltages is lower than the first of the two different voltages.

15. The method of claim 14 , wherein the first of the two different voltages is equal to the system input voltage of the first voltage plane.

16. The method of claim 14 , wherein the second of the two different voltages is derived from the system input voltage by a voltage drop across a diode or a linear regulator circuit.

17. The method of claim 14 , wherein the second of the two different voltages is equal to the system input voltage of the first voltage plane.

18. The method of claim 14 , wherein the second of the two different voltages is derived from the system input voltage from a voltage boost of the system input voltage.

19. The method of claim 18 , further comprising configuring the substrate to have a second voltage plane that receives the second of the two different voltages from the first voltage plane.

20. The method of claim 19 , further comprising connecting a Schottky diode between the first and second voltage planes to limit delays and voltage lags between the first and second voltage planes.

Assignments (15)
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 22, 2017
From: TOSHIBA CORPORATION
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043620/0430 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 14, 2016
From: OCZ STORAGE SOLUTIONS, INC.
To: TOSHIBA CORPORATION
Reel/Frame 038434/0371 →
RELEASE OF SECURITY INTEREST BY BANKRUPTCY COURT ORDER (RELEASES REEL/FRAME 030092/0739) Recorded Apr 8, 2014
From: HERCULES TECHNOLOGY GROWTH CAPITAL, INC.
To: OCZ TECHNOLOGY GROUP, INC.
Reel/Frame 032640/0284 →
RELEASE OF SECURITY INTEREST BY BANKRUPTCY COURT ORDER (RELEASES REEL/FRAME 031611/0168) Recorded Apr 8, 2014
From: COLLATERAL AGENTS, LLC
To: OCZ TECHNOLOGY GROUP, INC.
Reel/Frame 032640/0455 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE AND ATTACH A CORRECTED ASSIGNMENT DOCUMENT PREVIOUSLY RECORDED ON REEL 032365 FRAME 0920. ASSIGNOR(S) HEREBY CONFIRMS THE THE CORRECT EXECUTION DATE IS JANUARY 21, 2014. Recorded Mar 18, 2014
From: OCZ TECHNOLOGY GROUP, INC.
To: TAEC ACQUISITION CORP.
Reel/Frame 032461/0486 →
CHANGE OF NAME Recorded Feb 27, 2014
From: TAEC ACQUISITION CORP.
To: OCZ STORAGE SOLUTIONS, INC.
Reel/Frame 032365/0945 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 27, 2014
From: OCZ TECHNOLOGY GROUP, INC.
To: TAEC ACQUISITION CORP.
Reel/Frame 032365/0920 →
SECURITY AGREEMENT Recorded Nov 11, 2013
From: OCZ TECHNOLOGY GROUP, INC.
To: COLLATERAL AGENTS, LLC
Reel/Frame 031611/0168 →
SECURITY AGREEMENT Recorded Mar 27, 2013
From: OCZ TECHNOLOGY GROUP, INC.
To: HERCULES TECHNOLOGY GROWTH CAPITAL, INC.
Reel/Frame 030092/0739 →
RELEASE OF SECURITY INTEREST Recorded Mar 26, 2013
From: WELLS FARGO CAPITAL FINANCE, LLC, AS AGENT
To: OCZ TECHNOLOGY GROUP, INC.
Reel/Frame 030088/0443 →
SECURITY AGREEMENT Recorded May 14, 2012
From: OCZ TECHNOLOGY GROUP, INC.
To: WELLS FARGO CAPITAL FINANCE, LLC, AS AGENT
Reel/Frame 028440/0866 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 12, 2010
From: SCHUETTE, FRANZ MICHAEL; ALLEN, WILLIAM J.
To: OCZ TECHNOLOGY GROUP, INC.
Reel/Frame 023763/0908 →