Array substrate for electrophoresis type display device and method of manufacturing the same, method of repairing a line of the same
An array substrate for an electrophoresis type display device includes a plurality of gate lines on a substrate; a gate insulating layer on the plurality of gate lines; a plurality of data lines on the gate insulating layer and crossing the plurality of gate lines to define a plurality of pixel regions; a thin film transistor corresponding to each pixel region, the thin film transistor including a gate electrode, a semiconductor layer, and source and drain electrodes; a first passivation layer on the plurality of data lines; a second passivation layer on the first passivation layer, wherein the second passivation layer includes a first hole over the data line, and/or a second hole over the gate line with at least the gate insulating layer therebetween; and a pixel electrode on the second passivation layer and connected to the drain electrode, wherein a portion of the pixel electrode covers the first hole, and another portion of the pixel electrode covers the second hole. A method of manufacturing the same, and a method of repairing a line of the same is also disclosed.
1. An array substrate for an electrophoresis type display device, comprising:
a plurality of gate lines on a substrate;
a gate insulating layer on the plurality of gate lines;
a plurality of data lines on the gate insulating layer and crossing the plurality of gate lines to define a plurality of pixel regions;
a thin film transistor corresponding to each pixel region, the thin film transistor including a gate electrode, a semiconductor layer, and source and drain electrodes;
a first passivation layer on the plurality of data lines;
a second passivation layer on the first passivation layer, the second passivation layer including a first hole over the data line, and a second hole over the gate line;
a pixel electrode on the second passivation layer and connected to the drain electrode; and
an electrophoresis ink layer over the pixel electrode,
wherein a portion of the pixel electrode covers the first hole, and another portion of the pixel electrode covers the second hole,
wherein the second passivation layer entirely covers the pixel region, and
wherein the pixel electrode is disposed continuously over the first and second holes and the drain electrode.
2. The array substrate according to claim 1 , further comprising a third passivation layer comprising an inorganic insulating material and disposed between the pixel electrode and the second passivation layer.
3. The array substrate according to claim 1 , wherein:
each of the gate insulating layer and the first passivation layer comprises an inorganic insulating material; and
the second passivation layer comprises an organic insulating material.
4. The array substrate according to claim 3 , wherein a thickness of the second passivation layer is about 2 micrometers to about 4 micrometers.
5. An array substrate for an electrophoresis type display device, comprising:
a plurality of gate lines on a substrate;
a gate insulating layer on the plurality of gate lines;
a plurality of data lines on the gate insulating layer and crossing the plurality of gate lines to define a plurality of pixel regions;
a thin film transistor corresponding to each pixel region, the thin film transistor including a gate electrode, a semiconductor layer, and source and drain electrodes;
a first passivation layer on the plurality of data lines;
a second passivation layer on the first passivation layer, the second passivation layer including a first hole over the data line and a second hole over the gate line;
a pixel electrode on the second passivation layer and connected to the drain electrode; and
an electrophoresis ink layer over the pixel electrode,
wherein the pixel electrode covers the first hole or the second hole,
wherein the second passivation layer entirely covers the pixel region, and
wherein the pixel electrode is disposed continuously over the first and second holes and the drain electrode.
6. The array substrate according to claim 5 , further comprising a third passivation layer comprising an inorganic insulating material and disposed between the pixel electrode and the second passivation layer.
7. The array substrate according to claim 5 , wherein:
each of the gate insulating layer and the first passivation layer comprises an inorganic insulating material; and
the second passivation layer comprises an organic insulating material.
8. The array substrate according to claim 7 , wherein a thickness of the second passivation layer is about 2 micrometers to about 4 micrometers.