Semiconductor device having plural DRAM memory cells and a logic circuit and method for manufacturing the same
View Patent ↗A memory cell capacitor (C 3 ) of a DRAM is formed by use of a MIM capacitor which uses as its electrode a metal wiring line of the same layer (M 3 ) as metal wiring lines within a logic circuit (LOGIC), thereby enabling reduction of process costs. Higher integration is achievable by forming the capacitor using a high dielectric constant material and disposing it above a wiring layer in which bit lines (BL) are formed. In addition, using 2T cells makes it possible to provide a sufficient signal amount even when letting them operate with a low voltage. By commonizing the processes for fabricating capacitors in analog (ANALOG) and memory (MEM), it is possible to realize a semiconductor integrated circuit with the logic, analog and memory mounted together on one chip at low costs.
1. A semiconductor integrated circuit device comprising:
a semiconductor substrate having a main surface;
a first MISFET arranged at an analog circuit forming region of the main surface, wherein the first MISFET includes a source region and a drain region each formed in the semiconductor substrate, a gate insulating film formed on the semiconductor substrate and silicide layers formed on the source region, the drain region and the gate electrode;
a second MISFET arranged at a logic circuit forming region of the main surface, wherein the second MISFET includes a source region and a drain region each formed in the semiconductor substrate, a gate insulating film formed on the semiconductor substrate and silicide layers formed on the source region, the drain region and the gate electrode;
a first capacitor element having a lower electrode, a first insulating film formed on the lower electrode, and a higher electrode formed on the first insulating film, such that the higher electrode is formed over the semiconductor substrate;
a second insulating film formed over the first MISFET, the second MISFET and the first capacitor element; and
a second capacitor element arranged at the analog circuit forming region and formed over the second insulating film, wherein the second capacitor element has a lower electrode formed over the second insulating film, a third insulating film formed on the lower electrode, and a higher electrode formed on the third insulating film.
2. The semiconductor integrated circuit device according to claim 1 , wherein the lower electrode of the second capacitor element is formed on the same level layer as a wiring layer.
3. The semiconductor integrated circuit device according to claim 1 , wherein the lower electrode of the first capacitor element is formed on the same level layer as a wiring layer.
4. The semiconductor integrated circuit device according to claim 1 , wherein a thickness of the third insulating film of the second capacitor element is greater than a thickness of the first insulating film of the first capacitor element.
5. The semiconductor integrated circuit device according to claim 2 , wherein the wiring layer is comprised of a copper wiring layer.
6. The semiconductor integrated circuit device according to claim 1 , wherein the first capacitor element is comprised of a MIM capacitor.
7. A semiconductor integrated circuit device comprising:
a semiconductor substrate having a main surface;
a first MISFET arranged at a first circuit forming region of the main surface and constituting a first circuit, the first MISFET including a source region and a drain region each formed in the semiconductor substrate, a gate insulating film formed on the semiconductor substrate and silicide layers formed on the source region, the drain region and the gate electrode;
a second MISFET arranged at a logic circuit forming region of the main surface and constituting a second circuit different from the first circuit, the second MISFET including a source region and a drain region each formed in the semiconductor substrate, a gate insulating film formed on the semiconductor substrate and silicide layers formed on the source region, the drain region and the gate electrode;
a first capacitor element having a lower electrode, a first insulating film formed on the lower electrode, a higher electrode formed on the first insulating film, such that the higher electrode is formed over the semiconductor substrate;
a second insulating film formed over the first MISFET, the second MISFET and the first capacitor element; and
a second capacitor element arranged at the first circuit forming region and formed over the second insulating film, the second capacitor element having a lower electrode formed over the second insulating film, a third insulating film formed on the lower electrode, and a higher electrode formed on the third insulating film.
8. The semiconductor integrated circuit device according to claim 7 , wherein the lower electrode of the second capacitor element is formed on the same level layer as a wiring layer.
9. The semiconductor integrated circuit device according to claim 7 , wherein the lower electrode of the first capacitor element is formed on the same level layer as a wiring layer.
10. The semiconductor integrated circuit device according to claim 7 , wherein a thickness of the dielectric insulating film of the second capacitor element is greater than a thickness of the dielectric insulating film of the first capacitor element.
11. The semiconductor integrated circuit device according to claim 8 , wherein the wiring layer is comprised of a copper wiring layer.
12. The semiconductor integrated circuit device according to claim 7 , wherein the first capacitor element is comprised of a MIM capacitor.
13. The semiconductor integrated circuit device according to claim 7 , wherein the first circuit is an analog circuit and the second circuit is a logic circuit.