IP Library Granted Patent US 8,621,169
Granted Patent B2
US 8,621,169 · App. 12/635,208 · Granted Dec 31, 2013

Method for address space layout randomization in execute-in-place code

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Quick Facts
Patent No.
US 8,621,169
App. No.
12/635,208
Granted
Dec 31, 2013
Kind
B2
Abstract

A method for dynamically (i.e., upon boot) rewriting, in a failure resistant manner, of part of, or the entirety of, the flash memory for a device allows for a changing of location for logical blocks of execute-in-place code. Conveniently, the rewriting results in a randomization, of varying degree, of the address space layout upon each boot up cycle.

Claims (38)

1. A method of address space layout randomization for execute-in-place code, said method comprising:

storing an execute-in-place code image in a plurality of logical memory blocks occupying memory spaces having uniform dimensions;

provisioning, as a swap memory block, at least one memory space having said uniform dimensions, wherein said at least one memory space is among, and in addition to, said memory spaces storing said execute-in-place code;

maintaining a table of references to said plurality of logical memory blocks and said swap memory block;

receiving an indication of a boot; and

responsive to said receiving:

selecting a candidate logical memory block from among said plurality of logical memory blocks;

reading contents of a memory space occupied by said candidate logical memory block; and

writing said contents to said memory space provisioned as said swap memory block.

2. The method of claim 1 further comprising indicating, in said table, that a memory space occupied by said candidate logical memory block is pending erase.

3. The method of claim 1 further comprising indicating, in said table, that said candidate logical memory block occupies said memory space provisioned as said swap memory block.

4. The method of claim 1 further comprising storing, in correspondence with each logical memory block of said plurality of logical memory blocks, a signature.

5. The method of claim 4 further comprising obtaining said signature as a hash of contents of said each logical memory block.

6. The method of claim 5 wherein said writing further comprises obtaining a hash of said contents and comparing said hash against said signature.

7. The method of claim 1 further comprising:

receiving an indication of a subsequent boot; and

responsive to said receiving said indication of said subsequent boot:

identifying a candidate memory space pending erase; and

erasing said candidate memory space.

8. The method of claim 7 further comprising indicating, in said table, that said candidate memory space is said swap memory block.

9. A computing apparatus comprising a processor adapted to:

store an execute-in-place code image in a plurality of logical memory blocks occupying memory spaces having uniform dimensions;

provision, as a swap memory block, at least one memory space having said uniform dimensions, wherein said at least one memory space is among, and in addition to, said memory spaces storing said execute-in-place code;

maintain a table of references to said plurality of logical memory blocks and said swap memory block;

receive an indication of a boot; and

responsive to said receiving:

select a candidate logical memory block from among said plurality of logical memory blocks;

read contents of a memory space occupied by said candidate logical memory block; and

write said contents to said memory space provisioned as said swap memory block.

10. A non-transitory computer-readable medium containing computer-executable instructions that, when performed by a processor, cause said processor to:

store an execute-in-place code image in a plurality of logical memory blocks occupying memory spaces having uniform dimensions;

provision, as a swap memory block, at least one memory space having said uniform dimensions, wherein said at least one memory space is among, and in addition to, said memory spaces storing said execute-in-place code;

maintain a table of references to said plurality of logical memory blocks and said swap memory block;

receive an indication of a boot; and

responsive to said receiving:

select a candidate logical memory block from among said plurality of logical memory blocks;

read contents of a memory space occupied by said candidate logical memory block; and

write said contents to said memory space provisioned as said swap memory block.

Assignments (7)
NUNC PRO TUNC ASSIGNMENT Recorded Jun 19, 2023
From: BLACKBERRY LIMITED
To: MALIKIE INNOVATIONS LIMITED
Reel/Frame 064270/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 16, 2023
From: BLACKBERRY LIMITED
To: MALIKIE INNOVATIONS LIMITED
Reel/Frame 064104/0103 →
CHANGE OF NAME Recorded Nov 21, 2013
From: RESEARCH IN MOTION LIMITED
To: BLACKBERRY LIMITED
Reel/Frame 031693/0139 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 7, 2012
From: MCCALLUM, MICHAEL E.
To: RESEARCH IN MOTION LIMITED
Reel/Frame 027661/0530 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 27, 2012
From: RESEARCH IN MOTION UK LIMITED
To: RESEARCH IN MOTION LIMITED
Reel/Frame 027605/0276 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 28, 2011
From: WHITEHOUSE, OLIVER; WINSTON, BENJAMIN
To: RESEARCH IN MOTION UK LIMITED
Reel/Frame 027285/0825 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 11, 2009
From: WHITEHOUSE, OLIVER; WINSTON, BENJAMIN; MCCALLUM, MICHAEL E.
To: RESEARCH IN MOTION LIMITED
Reel/Frame 023643/0408 →