Method for manufacturing a power semiconductor device
View Patent ↗A method of manufacturing a power semiconductor device is provided. A first oxide layer is produced on a first main side of a substrate of a first conductivity type. A structured gate electrode layer with at least one opening is then formed on the first main side on top of the first oxide layer. A first dopant of the first conductivity type is implanted into the substrate on the first main side using the structured gate electrode layer as a mask, and the first dopant is diffused into the substrate. A second dopant of a second conductivity type is then implanted into the substrate on the first main side, and the second dopant is diffused into the substrate. After diffusing the first dopant into the substrate and before implanting the second dopant into the substrate, the first oxide layer is partially removed. The structured gate electrode layer can be used as a mask for implanting the second dopant.
1. A method of manufacturing a power semiconductor device, comprising:
forming a first oxide layer on a first main side of a substrate of a first conductivity type;
forming a gate electrode layer with at least one opening on the first main side on top of the first oxide layer,
forming an enhancement layer by implanting a first dopant of the first conductivity type into the substrate on the first main side using the formed gate electrode layer as a mask, and by diffusing the first dopant into the substrate; and
forming a base layer by implanting a second dopant of a second conductivity type into the substrate on the first main side, and by diffusing the second dopant into the substrate such that the base layer has a lower depth in a central area below the at least one opening, the depth of the base layer in the central area being shallower than a maximum depth to which the base layer extends in a peripheral area,
wherein the first oxide layer is partially removed after diffusing the first dopant into the substrate and before implanting the second dopant into the substrate, and the gate electrode layer is used as a mask for implanting the second dopant.
2. The method according to claim 1 , comprising removing the first oxide layer in areas in which the at least one opening of the gate electrode layer is arranged to form a gate oxide layer.
3. The method according to claim 1 , wherein the first dopant is at least one of phosphorous and arsenic ions.
4. The method according to claim 1 , wherein the first dopant is implanted with at least one of an energy of 40-150 keV and a dose of 1*1012-1 * 1014/cm2.
5. The method according to claim 1 , wherein the first dopant is diffused into the substrate to a depth of at least 1μm from an upper surface of the substrate.
6. The method according to claim 1 , wherein the second dopant is at least one of boron, aluminum, gallium and indium ions.
7. The method according to claim 1 , wherein the second dopant is implanted with at least one of an energy of 20-120 keV and a dose of 5* 10 13−3 *10 14 /cm2.
8. The method according to claim 1 , wherein the second dopant is diffused into the substrate to a maximum depth in a range between 0.5μm and 9μm from an upper surface of the substrate.
9. The method according to claim 2 , wherein the first dopant is at least one of phosphorous and arsenic ions.
10. The method according to claim 3 , wherein the first dopant is implanted with at least one of an energy of 40-150 keV and a dose of 1*10 12 −1 * 10 14 /cm2.
11. The method according to claim 1 , wherein the first dopant is diffused into the substrate to a depth in the range of 1μm to 10μm from an upper surface of the substrate.
12. The method according to claim 11 , wherein the first dopant is diffused into the substrate to a depth in the range of 1μm to 8μm from the upper surface of the substrate.
13. The method according to claim 11 , wherein the first dopant is diffused into the substrate to a depth in the range of 1μm to 6μm from the upper surface of the substrate.
14. The method according to claim 4 , wherein the first dopant is diffused into the substrate to a depth in the range of 1μm to 10μm from an upper surface of the substrate.
15. The method according to claim 6 , wherein the second dopant is implanted with at least one of an energy of 20-120 keV and a dose of 5* 10 13−3 *10 14 /cm2.
16. The method according to claim 7 , wherein the second dopant is diffused into the substrate to a maximum depth in a range between 0.5μm and 7μm from the upper surface of the substrate.
17. The method according to claim 8 , wherein the second dopant is diffused into the substrate to a maximum depth in a range between 0.5μm and 5μm from the upper surface of the substrate.
18. The method according to claim 15 , wherein the second dopant is diffused into the substrate to a maximum depth in a range between 0.5μm and 9μm from an upper surface of the substrate.
19. The method according to claim 1 , comprising: forming source regions of the first conductivity type on the first main side, the source regions being higher doped than the substrate.