Semiconductor device and data processor
To improve the speed of accessing a low-speed circuit block from a high-speed circuit block without significantly increasing power consumption. Ina data processor having a bus controller that performs timing control of access from the CPU operated in synchronization with a high-speed first clock signal to a peripheral circuit operated in synchronization with a low-speed second clock signal, a timing control circuit is provided between the peripheral circuit and the bus controller, and the bus controller causes, in response to a read instruction from the peripheral circuit, the timing control circuit to output data held by the peripheral circuit to the bus controller in synchronization with the cycle of the high-speed clock signal, causes the timing control circuit to start, in response to a write instruction directed to the peripheral circuit, writing into the peripheral circuit in synchronization with the cycle of the high-speed clock signal, and terminates the writing in synchronization with the cycle of the low-speed clock signal.
1. A semiconductor device comprising:
a first circuit operated in synchronization with a first clock signal;
a second circuit block operated in synchronization with a second clock signal having a frequency lower than that of the first clock signal;
a bridge circuit that performs timing control of access from the first circuit to the second circuit block; and
a third circuit block provided between the second circuit block and the bridge circuit to perform, based on an instruction from the bridge circuit, an operation of outputting data held by a storage circuit in the second circuit block to the bridge circuit in synchronization with the cycle of the first clock signal.
2. The semiconductor device according to claim 1 ,
wherein the bridge circuit starts, in response to an instruction of a read operation directed to the storage circuit from the first circuit, an output operation cycle to the bridge circuit by the third circuit block in synchronization with the cycle of the first clock signal, waits for a notice of completion of the output operation by the third circuit block, and terminates the output operation cycle.
3. The semiconductor device according to claim 2 ,
wherein the bridge circuit starts, in response to an instruction of a write operation directed to the storage circuit from the first circuit, a write operation into the storage circuit in synchronization with the cycle of the first clock signal, waits for a notice of completion of the write operation into the storage circuit synchronizing with the cycle of the second clock signal, and terminates the write operation cycle.
4. The semiconductor device according to claim 3 ,
wherein the first circuit is a CPU, further comprising an interrupt controller that outputs an interrupt signal to the first circuit in response to interrupt request from the second circuit block.
5. The semiconductor device according to claim 3 ,
wherein the second circuit block has a register circuit as the storage circuit, latch timing of the register circuit is controlled in synchronization with the second clock signal and selection timing of a latch output signal of the register circuit is synchronized with the second clock signal, and
wherein the third circuit block receives the latch output signal of the register circuit, and the selection timing of the received latch output signal is synchronized with the first clock signal.
6. The semiconductor device according to claim 3 ,
wherein the second circuit block is a clock synchronization type RAM that can operate as the storage circuit using the cycle of the second clock signal as a memory cycle, and
wherein the third circuit block has a latch circuit that latches the data read from the clock synchronization type RAM in synchronization with the second clock signal.
7. The semiconductor device according to claim 3 ,
wherein the second circuit block is a clock synchronization type RAM that can operate as the storage circuit using the cycle of the first clock signal as a memory cycle;
wherein the second circuit block operates the clock synchronization type RAM using the cycle of the second clock signal as a memory cycle; and
wherein the third circuit block operates the clock synchronization type RAM using the cycle of the first clock signal as a memory cycle.
8. A semiconductor device comprising:
a first circuit operated in synchronization with a first clock signal;
a second circuit block operated in synchronization with a second clock signal having a frequency lower than that of the first clock signal;
a bridge circuit that performs timing control of access from the first circuit to the second circuit block and has a first mode and a second mode; and
a third circuit block provided between the second circuit block and the bridge circuit,
wherein the bridge circuit, in the first mode, causes the third circuit block to output data held by a storage circuit within the second circuit block to the bridge circuit in synchronization with the cycle of the first clock signal and,
wherein the bridge circuit, in the second mode, causes the second circuit block to output data held by the storage circuit to the bridge circuit in synchronization with the cycle of the second clock signal.
9. The semiconductor device according to claim 8 ,
wherein in the first mode the bridge circuit starts, in response to an instruction of a read operation directed to the storage circuit from the first circuit, an output operation cycle to the bridge circuit by the third circuit block in synchronization with the cycle of the first clock signal, waits for a notice of completion of the output operation by the third circuit block, and terminates the output operation cycle.
10. The semiconductor device according to claim 9 ,
wherein in the first mode the bridge circuit starts, in response to an instruction of a write operation directed to the storage circuit from the first circuit, a write operation into the storage circuit in synchronization with the cycle of the first clock signal, waits for a notice of completion of the write operation into the storage circuit synchronizing with the cycle of the second clock signal, and terminates the write operation cycle.
11. The semiconductor device according to claim 10 ,
wherein the bridge circuit has a mode register that stores mode data for specifying which of the first mode or the second mode will be applied for each access target, and a bus access control unit that performs timing control of access in the mode based on the mode data stored in the mode register according to the access address from the first circuit.
12. The semiconductor device according to claim 11 ,
wherein the second circuit block has a register circuit as the storage circuit, latch timing of the register circuit is controlled in synchronization with the second clock signal, and selection timing of a latch output signal of the register circuit is synchronized with the second clock signal, and
wherein the third circuit block receives the latch output signal of the register circuit, and selection timing of the received latch output signal is synchronized with the first clock signal.
13. The semiconductor device according to claim 11 ,
wherein the second circuit block is a clock synchronization type RAM that can operate as the storage circuit using the cycle of the second clock signal as a memory cycle, and
wherein the third circuit block has a latch circuit that latches the data read from the clock synchronization type RAM in synchronization with the second clock signal.
14. The semiconductor device according to claim 11 ,
wherein the second circuit block is a clock synchronization type RAM that can operate as the storage circuit using the cycle of the first clock signal as a memory cycle;
wherein the second circuit block operates the clock synchronization type RAM using the cycle of the second clock signal as a memory cycle; and
wherein the third circuit block operates the clock synchronization type RAM using the cycle of the first clock signal as a memory cycle.
15. A data processor comprising:
a CPU operated in synchronization with a first clock signal;
a plurality of peripheral circuits operated in synchronization with a second clock signal having a frequency lower than that of the first clock signal;
a bus controller that performs timing control of access from the CPU to the peripheral circuits; and
a timing control circuit that is provided between the peripheral circuits and the bus controller and performs an operation of outputting data held by the peripheral circuits to the bus controller based on an instruction from the bus controller in synchronization with the cycle of the first clock signal.
16. The data processor according to claim 15 , further comprising an interrupt controller that outputs an interrupt signal to the CPU in response to an interrupt request from the peripheral circuit.
17. The data processor according to claim 16 ,
wherein the bus controller starts, in response to an instruction of a read operation directed to the peripheral circuit from the CPU, an output operation cycle to the bus controller by the timing control circuit in synchronization with the cycle of the first clock signal, waits for a notice of completion of the output operation by the timing control circuit, and terminates the output operation cycle.
18. The data processor according to claim 17 ,
wherein the bus controller starts, in response to an instruction of a write operation directed to the peripheral circuit from the CPU, a write operation into the peripheral circuit in synchronization with the cycle of the first clock signal, waits for a notice of completion of the write operation into the peripheral circuit synchronizing with the cycle of the second clock signal, and terminates the write operation cycle.
19. A data processor comprising:
a CPU operated in synchronization with a first clock signal;
a plurality of peripheral circuits operated in synchronization with a second clock signal having a frequency lower than that of the first clock signal;
a bus controller that performs timing control of access from the CPU to the peripheral circuits; and
a timing control circuit that is provided between the peripheral circuits and the bus controller,
wherein the bus controller causes the timing control circuit to output data held by the peripheral circuits to the bus controller in synchronization with the cycle of the first clock signal in response to a read instruction from the peripheral circuit, causes the timing control circuit to start writing into the peripheral circuits in synchronization with the cycle of the first clock signal in response to a write instruction into the peripheral circuits, and terminates the writing in synchronization with the cycle of the second clock signal.