Granted Patent B2

US 9,026,401 · App. 12/636,673 · Granted May 5, 2015

Abstract

Claims (43)

1. A method comprising:

monitoring one or more parameters on at least one respective memory module using an electronic apparatus that includes a differential pair of transistors configuration coupled between a power supply and ground potential and coupled to an output node, the differential pair of transistors configuration being housed on the respective memory module and wherein the differential pair of transistors configuration is operable to provide at the output node an inverted chip select output signal relative to a chip select input signal;

using a voltage divider coupled to a base of a second transistor of the differential pair and operable to provide as a reference signal a programmable reference voltage between zero and an operating voltage of the respective memory module;

using a first resistor configurable to be coupled to the base of the second transistor and the voltage divider;

using a second resistor configurable to be coupled to the base of the second transistor, and further coupled to a preselected reference voltage, wherein the first resistor is installed when the programmable reference voltage is applied and the second resistor is installed when the preselected reference voltage is applied; and

transmitting corresponding parameter information away from the respective memory module to a device that is external to the respective memory modules, wherein the device only functions to display the monitored behavior of the respective memory module.

2. The method of claim 1 , further comprising:

detecting and receiving respective chip select input signals on the respective memory modules that are being monitored;

comparing each of the respective input signals to a corresponding threshold value; and

generating respective output signals based on comparing the respective input signals to the corresponding threshold value, wherein the output signals form at least a subset of the parameter information.

3. The method of claim 2 , wherein the corresponding threshold value is programmable.

4. The method of claim 2 , further comprising buffering the respective output signals.

5. The method of claim 2 , further comprising using at least one differential pair of transistors for each respective memory module that is being monitored, wherein the differential pair of transistors is configured as a comparator.

6. The method of claim 2 , further comprising using a voltage divider for each respective memory module that is being monitored to vary the corresponding threshold value.

7. The method of claim 1 , further comprising displaying the parameter information on the device that is external to the respective memory modules, wherein the parameter information includes at least a subset of temperature measurement, inverted chip select output signals, a memory module clock signal, and power supply information for each respective memory module that is being monitored.

8. The method of claim 1 , wherein transmitting corresponding parameter information away from the respective memory module further comprises routing the parameter information to a respective connector associated with each respective memory module that is being monitored.

9. The method of claim 1 , further comprising aggregating the parameter information from the two or more of the respective memory modules.

10. The method of claim 1 , wherein transmitting corresponding parameter information away from the respective memory module comprises transmitting the corresponding parameter information wirelessly.

11. An apparatus comprising:

a power supply and ground potential;

a connector node coupled to an output node; and

a differential pair of transistors configuration coupled between the power supply and ground potential and coupled to the output node,

wherein, the differential pair of transistors configuration is operable to provide at the output node an inverted chip select output signal relative to a chip select input signal; and

wherein, the differential pair of transistors configuration is housed on a memory module;

a voltage divider coupled to a base of a second transistor of the differential pair and operable to provide as a reference signal a programmable reference voltage between zero and an operating voltage of the memory module;

a first resistor configurable to be coupled to the base of the second transistor and the voltage divider; and

a second resistor configurable to be coupled to the base of the second transistor, and further coupled to a preselected reference voltage,

wherein the first resistor is installed when the programmable reference voltage is applied; and

wherein the second resistor is installed when the preselected reference voltage is applied.

12. The apparatus of claim 11 , further comprising at least a subset of:

a temperature measuring device coupled to the connector node, the temperature measuring device being operable to measure the temperature of the memory module; and

a clock divider circuit coupled to the connector node, the clock divider circuit being operable to divide a received memory module clock signal.

13. The apparatus of claim 12 , wherein the connector node is coupled to an accessory device, the accessory device being configured to receive parameter information of the memory module, and operable to provide a representation of the received parameter information.

14. The apparatus of claim 13 , wherein the accessory device is configured to receive as parameter information of the memory module, at least a subset of temperature measurements from the temperature measuring device, the inverted chip select output signal of each of the plurality of chip select signals, the memory module clock signal, and power supply information from the memory module.

15. The apparatus of claim 13 further comprising a display device coupled to the accessory device, wherein the representation of the received parameter information is displayed on the display device associated with the accessory device.

16. The apparatus of claim 13 further comprising a host interface configured to associate with a computing device, wherein the computing device is configured to process the received parameter information of the memory module.

17. The apparatus of claim 11 , wherein the differential pair of transistors configuration further comprises:

a first transistor coupled to the power supply, and having an emitter, base and collector, wherein the base of the first transistor is configured to receive a chip select input signal from a plurality of chip select signals and the collector of the first transistor is coupled to the output node;

the second transistor, coupled in parallel to the first transistor and having an emitter, base and collector, wherein the base of the second transistor is configured to receive a reference signal, the emitter of the second transistor is coupled to the emitter of the first transistor, and the collector of the second transistor is coupled to ground; and

a resistive element coupled in series with the collector of the first transistor and coupled to the ground potential.

18. The apparatus of claim 11 , further comprising an impedance component coupled to the power supply and to the differential pair of transistors configuration, wherein the impedance component is from at least a subset of a resistor, transistor, and capacitor.

19. The apparatus of claim 11 , further comprising a plurality of memory modules, wherein each memory module includes at least one of the differential pair of transistors configuration.

20. The apparatus of claim 11 , further comprising a display device coupled to the connector node, the display device configured to receive the inverted chip select output signal of each of the plurality of chip select signals, and operable to display a representation of the received inverted chip select output signals.

Assignments (8)