IP Library Granted Patent US 7,860,152
Granted Patent B2
US 7,860,152 · App. 12/638,468 · Granted Dec 28, 2010

Wireless communications system with secondary synchronization code based on values in primary synchronization code

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Quick Facts
Patent No.
US 7,860,152
App. No.
12/638,468
Granted
Dec 28, 2010
Kind
B2
Abstract

A wireless communication system. The system comprises transmitter circuitry (BST 1 ), the transmitter circuitry comprising encoder circuitry ( 50 ) for transmitting a plurality of frames (FR). Each of the plurality of frames comprises a primary synchronization code (PCS) and a secondary synchronization code (SSC). The encoder circuitry comprises of circuitry ( 50 1 ) for providing the primary synchronization code in response to a first sequence ( 32 ). The encoder circuitry further comprises circuitry ( 50 2 ) for providing the secondary synchronization code in response to a second sequence ( 54 ) and a third sequence ( 56 ). The second sequence is selected from a plurality of sequences. Each of the plurality of sequences is orthogonal with respect to all other sequences in the plurality of sequences. The third sequence comprises a subset of bits from the first sequence.

Claims (10)

1. A process of generating synchronization code signals comprising:

A. providing a primary synchronization code of a generalized hierarchical Golay sequence in a first pattern of 256 bits, the first pattern being formed of 8-bit values A, B, −A and −B, in which the value A represents a pattern of real values A={1, 1, 1, 1, 1, 1, −1, −1}, the value B represents a pattern of real values B={1, −1, 1, −1, 1, −1, −1, 1}, and the first pattern of the primary synchronization code being {A, B, A, B, A, B, −A, −B, −A, −B, A, B, −A, −B, −A, −B, A, B, A, B, A, B, −A, −B, A, B, −A, −B, A, B, A, B};

B. generating a primary synchronization code signal from the primary synchronization code;

C. providing a secondary synchronization code of 256 bits by exclusive OR combining a second pattern of bits and a third pattern of bits separate from the first pattern of bits, the first pattern of bits, the second pattern of bits and the third pattern of bits being different from one another,

i. the providing a secondary synchronization code including selecting a subset of a set of Hadamard codes to be the second pattern, deriving the set of Hadamard codes by combining sequences of Walsh codes, selecting for the subset the Hadamard codes that are orthogonal with one another, and selecting the subset to be every Nth code of the set of Hadamard codes, and

ii. the providing a secondary synchronization code including selecting values of bits from the first pattern to be the third pattern; and

D. generating a secondary synchronization code signal from the secondary synchronization code.

2. The process of claim 1 in which the selecting a subset of a set of Hadamard codes includes selecting 16 Hadamard codes prior to harmonization, and 15 Hadamard codes after harmonization, from 17 Hadamard codes, ordering the Hadamard codes of the subset in a particular sequence, and selecting repeated ones of the 17 Hadamard codes for the subset.

3. The process of claim 1 in which the number N is eight.

4. The process of claim 1 in which selecting values of bits from the first pattern to be the third pattern includes repeating the value A 32 times.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 14, 2020
From: INTEL CORPORATION
To: APPLE INC.
Reel/Frame 052414/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 19, 2017
From: TEXAS INSTRUMENTS INCORPORATED
To: INTEL CORPORATION
Reel/Frame 041383/0040 →