Semiconductor device and method for fabricating the same
View Patent ↗A semiconductor device including a conductive layer, a diffusion barrier layer formed over the conductive layer, including a refractory metal compound, and acquired after a surface treatment, and a metal silicide layer formed over the diffusion barrier layer. The adhesion between a diffusion barrier layer and a metal silicide layer may be improved by increasing the surface energy of the diffusion barrier layer through a surface treatment. Therefore, although the metal silicide layer is fused in a high-temperature process, it is possible to prevent a void from being caused at the interface between the diffusion barrier layer and the metal silicide layer. Moreover, it is possible to increase the adhesion between a conductive layer and the diffusion barrier layer by increasing the surface energy of the conductive layer through the surface treatment.
1. A semiconductor device, comprising:
a conductive layer;
a diffusion barrier layer, including a refractory metal compound, formed over the conductive layer, the diffusion barrier layer including a surface region and a non-surface region, wherein the surface region and the non-surface region are chemically identical but have different physical structures; and
a metal silicide layer formed over the diffusion barrier layer, wherein the surface region of the diffusion barrier layer is in direct contact with the metal silicide layer.
2. The semiconductor device of claim 1 , wherein the physical structure of the surface region of the diffusion barrier layer causes the surface region of the diffusion layer to have a greater surface energy than a surface energy of the non-surface region of the diffusion barrier layer.
3. The semiconductor device of claim 1 , wherein the conductive layer includes a surface region, which is in direct contact with the diffusion barrier layer, and a non-surface region, and wherein the surface region of the conductive layer and the non-surface region of the conductive layer are chemically identical but have different physical structures.
4. The semiconductor device of claim 3 , wherein the physical structure of the surface region of the conductive layer causes the surface region of the conductive layer to have a greater surface energy than a surface energy of the non-surface region of the conductive layer.
5. The semiconductor device of claim 1 , wherein an interface region, formed between the diffusion barrier layer and the metal silicide layer, forms an ohmic contact between the diffusion barrier layer and the metal silicide layer due to a surface energy of the surface region of the diffusion barrier layer.
6. The semiconductor device of claim 1 , wherein the diffusion barrier layer includes a metal layer containing nitrogen.
7. A gate pattern of a semiconductor device, the gate pattern comprising:
a gate electrode;
a diffusion barrier layer, including a refractory metal compound, formed over the gate electrode, the diffusion barrier layer including a surface region and a non-surface region, wherein the surface region and the non-surface region are chemically identical but have different physical structures; and
a metal silicide layer formed over the diffusion barrier layer, wherein the surface region of the diffusion barrier layer is in direct contact with the metal silicide layer.
8. The gate pattern of claim 7 , wherein the physical structure of the surface region of the diffusion barrier layer causes the surface region of the diffusion layer to have a greater surface energy than a surface energy of the non-surface region of the diffusion barrier layer.
9. The gate pattern of claim 8 , wherein the gate electrode includes a surface region, which is in direct contact with the diffusion barrier layer, and a non-surface region, and wherein the surface region of the gate electrode and the non-surface region of the gate electrode are chemically identical but have different physical structures.
10. The gate pattern of claim 7 , wherein the physical structure of the surface region of the gate electrode causes the surface region of the gate electrode to have a greater surface energy than a surface energy of the non-surface region of the gate electrode.
11. The gate pattern of claim 7 , wherein an interface region, formed between the diffusion barrier layer and the metal silicide layer, forms an ohmic contact between the diffusion barrier layer and the metal silicide layer due to a surface energy of the surface region of the diffusion barrier layer.
12. The gate pattern of claim 7 , wherein the diffusion barrier layer includes a metal layer containing nitrogen.
13. The gate pattern of claim 7 , further comprising:
a gate insulation layer interposed between a substrate and the gate electrode.
14. The gate pattern of claim 7 , further comprising:
a tunnel insulation layer formed over a substrate;
a charge trapping layer or a charge storage layer formed over the tunnel insulation layer; and
a charge blocking layer formed between the charge trapping layer or the charge storage layer and the gate electrode.