Apparatus and method with controlled switch method
View Patent ↗An embedded microcontroller system comprises a central processing unit, a system controller for receiving and handling an interrupt, a register having storage locations containing sets of predefined system data for different operating conditions of the system assigned to the interrupts coupled to set a system configuration. The system data in the register is defined and stored before receipt of an interrupt. On receipt of an interrupt the system controller transmits a selection signal to the register. The register selects a predefined storage location assigned to the received interrupt. The corresponding system configuration data is used to control system configuration of the embedded microcontroller system, such as allocation of CPU time to virtual CPUs and selection of clock frequency or power voltage for modules.
1. An embedded microcontroller system comprising:
a central processing unit operable to set said embedded microcontroller system in one of a plurality of system configurations;
a system controller for receiving and handling interrupts including generating a selection signal corresponding to a received interrupt;
a register set connected to said system controller and said central processing unit, said register set having plural storage locations, each storage location assigned to a corresponding interrupt and containing a set of predefined system data for different system configurations of said embedded microcontroller system, said register set responsive to a selection signal from said system controller to recall said set of predetermined system data corresponding to said selection signal for setting a corresponding system configuration via said central processing unit.
2. The embedded microcontroller system of claim 1 , wherein:
said set of registers includes at least one lock mode protecting at least part of said set of predefined system data from modification and an unlock mode permitting modification of said set of predefined system data.
3. The embedded microcontroller system of claim 1 , wherein:
said sets of predetermined system data include data for configuration of system clock distribution for system resources and tasks.
4. The embedded microcontroller system of claim 3 , wherein:
said central processing unit includes a plurality of virtual central processing units each allocated a predetermined portion of time of said central processing unit; and
said predetermined system data for configuration of system clock distribution for system resources and tasks includes data for allocation of central processing unit time to said plurality of virtual central processing units.
5. The embedded microcontroller system of claim 4 , further comprising:
a plurality of independently powered power supply domains; and
said predetermined system data for configuration of system clock distribution for system resources and tasks includes data controlling a power supply voltage for each power supply domain.
6. The embedded microcontroller system of claim 5 , wherein:
said data controlling a power supply voltage for each power supply domain includes data for powering up at least one power supply domain.
7. The embedded microcontroller system of claim 5 , wherein:
said data controlling a power supply voltage for each power supply domain includes data for powering down at least one power supply domain.
8. The embedded microcontroller system of claim 1 , wherein:
said sets of predetermined system data include data for setting a system clock frequency; and
wherein the embedded microcontroller system further comprises:
a plurality of independently powered clocked clock domains; and
said predetermined system data for configuration of system clock frequency includes data controlling a clock frequency for each clock domain.
9. The embedded microcontroller system of claim 1 , wherein:
said sets of predefined system data include data selecting safe operation conditions; and
the embedded microcontroller system further comprises:
a watchdog timer having a selectable duration time,
said central processing unit is connected to said watchdog timer and responsive to expiration of said duration time of said watchdog timer, and
said data selecting safe operating conditions includes data selecting a delay time for said watchdog timer.
10. The embedded microcontroller system of claim 1 , wherein:
said sets of predetermined system data include data identifying an entity within said embedded microcontroller system to processes a request triggered by said interrupt.
11. The embedded microcontroller system of claim 10 , wherein:
said sets of predetermined system data include data identifying a previous entity.
12. The embedded microcontroller system of claim 1 , wherein:
said sets of predetermined system data include secure mode data to enable data encryption and decryption.
13. The embedded microcontroller system of claim 1 , further comprising:
a register having storage locations containing at least a present entity identifier that indicates a present master in said embedded microcontroller system; and
a resource within said embedded microcontroller system coupled to the register, said resource storing an entity identifier of an entity permitted to use the resource and including a logic circuit comparing the present entity identifier from said register with said stored entity identifier to determine whether said present entity can use said resource.
14. A method of configuring an embedded microcontroller system, comprising the steps of:
assigning a set of predefined system data for an operating condition of the embedded microcontroller system to an interrupt;
storing the set of predefined system data in a register before receipt of the interrupt;
receiving the interrupt;
selecting a predefined storage location of the register containing the set of predefined system data corresponding to the received interrupt; and
setting a system configuration within the embedded microcontroller corresponding to the selected predefined system data.