Comparator circuit for comparing three inputs
View Patent ↗A comparator circuit. A comparator circuit may include a differential amplifying unit to amplify a difference between a voltage at a first node and a voltage at a second node and/or output a resultant voltage, and/or a current source to supply a first bias current to a first node and/or supply a second bias current to a second node. A comparator may include a first bias switch to bias a current flowing from a first node to a ground voltage source, a second bias switch to bias a part of a current flowing from a second node to a ground voltage source, a third bias switch to bias a remaining part of a current flowing from a second node to a ground voltage source, and/or a bias converting unit to supply a third bias current to a second node.
1. An apparatus comprising:
a differential amplifying unit configured to amplify a difference between a voltage at a first node and a voltage at a second node, and to output a resultant voltage;
a current source configured to supply a first bias current to said first node and supply a second bias current to said second node;
a first bias switch configured to bias a current flowing from said first node to a ground voltage source based on a first voltage;
a second bias switch configured to bias a part of a current flowing from said second node to said ground voltage source based on a second voltage;
a third bias switch configured to bias a remaining part of said current flowing from said second node to said ground voltage source based on a third voltage; and
a bias converting unit configured to supply a third bias current to said second node based on said second voltage and said third voltage.
2. The apparatus of claim 1 , wherein said differential amplifying unit comprises at least one of a plurality of output loads and a plurality of differential amplifiers.
3. The apparatus of claim 1 , wherein said first bias current and said second bias current comprise substantially the same value.
4. The apparatus of claim 1 , wherein said bias converting unit is configured to supply said third bias current to said second node when said second voltage and said third voltage are within a predetermined range.
5. The apparatus of claim 1 , wherein said bias converting unit comprises:
a first comparator configured to compare said second voltage with a first division voltage divided from said third voltage and to output a first comparison signal based on a result of said comparison;
a second comparator configured to compare said third voltage with a second division voltage divided from said second voltage and to output a second comparison signal based on a result of said comparison;
an inverter configured to invert said second comparison signal;
a NAND gate configured to logically operate said first comparison signal and an output from said inverter, and to output a result of said logical operation; and
a bias converting transistor configured to supply said third bias current to said second node based on an output from said NAND gate.
6. The apparatus of claim 1 , wherein said bias converting unit comprises:
a first comparator configured to compare said second voltage with a first division voltage divided from said third voltage, and to output a first comparison signal based on a result of said comparison;
a second comparator configured to compare said third voltage with a second division voltage divided from said second voltage, and to output a second comparison signal based on a result of said comparison; and
a switching unit configured to supply said third current to said second node based on said first and second comparison signals.
7. The apparatus of claim 1 , comprising a comparator circuit.
8. An apparatus comprising:
a differential amplifying unit configured to amplify a difference between a voltage at a first node and a voltage at a second node, and to output a resultant voltage;
a first bias switch configured to control a current flowing to a ground voltage source from a first node to which a first current is supplied based on a first voltage;
a second bias switch configured to control a part of a current flowing to said ground voltage source from said second node to which a second current is supplied based on a second voltage;
a third bias switch configured to control a remaining part of a current flowing from said second node to said ground voltage source based on a third voltage; and
a bias converting unit configured to supply a third bias current to said second node based on said second voltage and said third voltage.
9. The apparatus of claim 8 , wherein said differential amplifying unit comprises at least one of a plurality of output loads and a plurality of differential amplifiers.
10. The apparatus of claim 8 , wherein:
said first bias switch comprises a bipolar transistor connected between said first node and said ground voltage source while having a first base to which said first voltage is applied;
said second bias switch comprises a bipolar transistor connected between said second node and said ground voltage source while having a second base to which said second voltage is applied;
said third bias switch comprises a bipolar transistor connected between said second node and said ground voltage source while having a third base to which said third voltage is applied.
11. The apparatus of claim 8 , wherein said bias converting unit comprises:
a first comparator configured to compare said second voltage with a first division voltage divided from said third voltage, and to output a first comparison signal based on a result of said comparison;
a second comparator configured to compare said third voltage with a second division voltage divided from said second voltage, and to output a second comparison signal based on a result of said comparison;
a logical operating unit configured to logically operate said first and second comparison signals, and to output a result of said logical operation; and
a bias converting transistor configured to supply said third bias current to said second node based on an output from said logical operating unit.
12. The apparatus of claim 8 , wherein said bias converting unit comprises a switching unit.
13. The apparatus of claim 8 , comprising a comparator circuit.
14. An method comprising:
forming a differential amplifying unit to amplify a difference between a voltage at a first node and a voltage at a second node, and output a resultant voltage;
forming a current source to supply a first bias current to said first node and supply a second bias current to said second node;
forming a first bias switch to bias a current flowing from said first node to a ground voltage source based on a first voltage;
forming a second bias switch to bias a part of a current flowing from said second node to said ground voltage source based on a second voltage;
forming a third bias switch to bias a remaining part of said current flowing from said second node to said ground voltage source based on a third voltage; and
forming a bias converting unit to supply a third bias current to said second node based on said second voltage and said third voltage.
15. The method of claim 14 , wherein said differential amplifying unit comprises at least one of a plurality of output loads and a plurality of differential amplifiers.
16. The method of claim 14 , wherein said first bias current and said second bias current comprise substantially the same value.
17. The method of claim 14 , wherein said bias converting unit is configured to supply said third bias current to said second node when said second voltage and said third voltage are within a predetermined range.
18. The method of claim 14 , wherein, said bias converting unit comprises:
a first comparator configured to compare said second voltage with a first division voltage divided from said third voltage and to output a first comparison signal based on a result of said comparison;
a second comparator configured to compare said third voltage with a second division voltage divided from said second voltage and to output a second comparison signal based on a result of said comparison;
an inverter configured to invert said second comparison signal;
a NAND gate configured to logically operate said first comparison signal and an output from said inverter, and to output a result of said logical operation; and
a bias converting transistor configured to supply said third bias current to said second node based on an output from said NAND gate.
19. The method of claim 14 , wherein said bias converting unit comprises:
a first comparator configured to compare said second voltage with a first division voltage divided from said third voltage, and to output a first comparison signal based on a result of said comparison;
a second comparator configured to compare said third voltage with a second division voltage divided from said second voltage, and to output a second comparison signal based on a result of said comparison; and
a switching unit configured to supply said third current to said second node based on said first and second comparison signals.
20. The method of claim 14 , comprising forming a comparator circuit.