Reducing implementation costs of communicating cache invalidation information in a multicore processor

1. A processor, comprising:

a plurality of hardware processor cores, each comprising a respective higher-level cache, wherein each higher-level cache comprises a plurality of higher-level cache lines; and

a hardware lower-level cache comprising a plurality of lower-level cache lines, wherein each of the lower-level cache lines is configured to store data that corresponds to multiple higher-level cache lines;

wherein in response to invalidating a given one of the lower-level cache lines, the lower-level cache is configured to convey a sequence of invalidation packets to the plurality of processor cores via an interface, wherein each member of the sequence of invalidation packets corresponds to a respective higher-level cache line to be invalidated, and wherein the sequence of invalidation packets comprises a total of N bits, and wherein the interface has a bit-width of less than N bits; and

wherein each of the invalidation packets comprises invalidation information indicative of a location of the respective higher-level cache line within different ones of the processor cores.

2. The processor as recited in claim 1 , further comprising an interconnect network coupled to exchange information between individual ones of the processor cores and the lower-level cache, wherein the interconnect network is configured to:

receive a given invalidation packet from the lower-level cache;

split the invalidation information included within the given invalidation packet into a plurality of portions, wherein each of the portions corresponds to a respective group that includes fewer than all of the processor cores;

for each given one of the portions, convey a distinct invalidation packet including the given portion to processor cores that are members of the respective group corresponding to the given portion, without conveying the distinct invalidation packet to processor cores that are not members of the respective group corresponding to the given portion.

3. The processor as recited in claim 2 , wherein the processor cores are physically distributed around at least two opposite sides of the interconnect network.

4. The processor as recited in claim 3 , wherein the lower-level cache comprises a plurality of banks, and wherein the banks are also physically distributed around the at least two opposite sides of the interconnect network.

5. The processor as recited in claim 1 , wherein the lower-level cache is configured as a second-level (L2) cache, and wherein the higher-level caches are configured as first-level (L1) caches.

6. The processor as recited in claim 1 , wherein for a particular processor core, the respective higher-level cache is configured as a set-associative cache comprising multiple ways, and wherein the invalidation information included in the invalidation packet is configured to indicate which one of the ways stores the higher-level cache line to be invalidated within the particular processor core.

7. The processor as recited in claim 1 , wherein each of the processor cores comprises multiple higher-level caches, and wherein the invalidation information included in the invalidation packet for a particular processor core is configured to indicate which one of the multiple higher-level caches stores the higher-level cache line to be invalidated within the particular processor core.

8. A method, comprising:

a hardware lower-level cache detecting an invalidation of a given one of a plurality of lower-level cache lines of the lower-level cache;

in response to detecting the invalidation of the given lower-level cache line, the lower-level cache conveying a sequence of invalidation packets to a plurality of hardware processor cores via an interface, wherein each of the processor cores comprises a respective higher-level cache, wherein each higher-level cache comprises a plurality of higher-level cache lines, and wherein each of the lower-level cache lines is configured to store data that corresponds to multiple higher-level cache lines;

wherein each member of the sequence of invalidation packets corresponds to a respective higher-level cache line to be invalidated, and wherein the sequence of invalidation packets comprises a total of N bits, and wherein the interface has a bit-width of less than N bits; and

wherein each of the invalidation packets comprises invalidation information indicative of a location of the respective higher-level cache line within different ones of the processor cores.

9. The method as recited in claim 8 , further comprising:

an interconnect network receiving a given invalidation packet from the lower-level cache;

the interconnect network splitting the invalidation information included within the given invalidation packet into a plurality of portions, wherein each of the portions corresponds to a respective group that includes fewer than all of the processor cores; and

for each given one of the portions, the interconnect network conveying a distinct invalidation packet including the given portion to processor cores that are members of the respective group corresponding to the given portion, without conveying the distinct invalidation packet to processor cores that are not members of the respective group corresponding to the given portion.

10. The method as recited in claim 9 , wherein the processor cores are physically distributed around at least two opposite sides of the interconnect network.

11. The method as recited in claim 10 , wherein the lower-level cache comprises a plurality of banks, and wherein the banks are also physically distributed around the at least two opposite sides of the interconnect network.

12. The method as recited in claim 8 , wherein the lower-level cache is configured as a second-level (L2) cache, and wherein the higher-level caches are configured as first-level (L1) caches.

13. The method as recited in claim 8 , wherein for a particular processor core, the respective higher-level cache is configured as a set-associative cache comprising multiple ways, and wherein the invalidation information included in the invalidation packet is configured to indicate which one of the ways stores the higher-level cache line to be invalidated within the particular processor core.

14. The method as recited in claim 8 , wherein each of the processor cores comprises multiple higher-level caches, and wherein the invalidation information included in the invalidation packet for a particular processor core is configured to indicate which one of the multiple higher-level caches stores the higher-level cache line to be invalidated within the particular processor core.

15. A system, comprising:

a system memory; and

a processor coupled to the system memory, wherein the processor comprises:

a plurality of hardware processor cores, each comprising a respective higher-level cache, wherein each higher-level cache comprises a plurality of higher-level cache lines; and

a hardware lower-level cache comprising a plurality of lower-level cache lines, wherein each of the lower-level cache lines is configured to store data that corresponds to multiple higher-level cache lines;

wherein in response to invalidating a given one of the lower-level cache lines, the lower-level cache is configured to convey a sequence of invalidation packets to the plurality of processor cores via an interface, wherein each member of the sequence of invalidation packets corresponds to a respective higher-level cache line to be invalidated, and wherein the sequence of invalidation packets comprises a total of N bits, and wherein the interface has a bit-width of less than N bits; and

wherein each of the invalidation packets comprises invalidation information indicative of a location of the respective higher-level cache line within different ones of the processor cores.

16. The system as recited in claim 15 , wherein the processor further comprises an interconnect network coupled to exchange information between individual ones of the processor cores and the lower-level cache, wherein the interconnect network is configured to:

receive a given invalidation packet from the lower-level cache;

split the invalidation information included within the given invalidation packet into a plurality of portions, wherein each of the portions corresponds to a respective group that includes fewer than all of the processor cores;

for each given one of the portions, convey a distinct invalidation packet including the given portion to processor cores that are members of the respective group corresponding to the given portion, without conveying the distinct invalidation packet to processor cores that are not members of the respective group corresponding to the given portion.

17. The system as recited in claim 16 , wherein the processor cores are physically distributed around at least two opposite sides of the interconnect network.

18. The system as recited in claim 17 , wherein the lower-level cache comprises a plurality of banks, and wherein the banks are also physically distributed around the at least two opposite sides of the interconnect network.

19. The system as recited in claim 15 , wherein for a particular processor core, the respective higher-level cache is configured as a set-associative cache comprising multiple ways, and wherein the invalidation information included in the invalidation packet is configured to indicate which one of the ways stores the higher-level cache line to be invalidated within the particular processor core.

20. The system as recited in claim 15 , wherein each of the processor cores comprises multiple higher-level caches, and wherein the invalidation information included in the invalidation packet for a particular processor core is configured to indicate which one of the multiple higher-level caches stores the higher-level cache line to be invalidated within the particular processor core.