Flash memory device and method of fabricating the same
View Patent ↗A flash memory device and a method for fabricating the same are disclosed. The flash memory device includes an ONO layer on a substrate, polysilicon gates on the ONO layer, a gate oxide layer on the substrate, the ONO layer and the polysilicon gates, and a low temperature oxide layer and polysilicon sidewall spacers on outer side surfaces of the polysilicon gates, except in a region between nearest adjacent polysilicon gates.
1. A method for fabricating a flash memory device comprising:
forming an ONO layer and a first polysilicon layer on a substrate;
patterning the first polysilicon layer and the ONO layer to form a plurality of floating gates;
forming a gate oxide layer on or over the substrate and the plurality of floating gates;
forming a resin on the substrate having the gate oxide layer thereon;
removing a portion of the resin to expose the gate oxide layer, keeping a region between adjacent floating gates filled with the resin;
removing the resin exposed by a photoresist pattern over resin between nearest adjacent floating gates;
forming a second polysilicon layer on or over the floating gates and the resin;
forming sidewall spacers on outer surfaces of the gate oxide by etching the second polysilicon layer; and
removing the remaining resin between the nearest adjacent floating gates.
2. The method of claim 1 , wherein the resin comprises a novolak resin.
3. The method of claim 2 , wherein removing the resin comprises patterning and developing a photoresist such that a photoresist pattern is formed over the resin between the nearest adjacent floating gates.
4. The method of claim 3 , further comprising:
forming a low temperature oxide layer on the substrate having the resin between the nearest adjacent floating gates.
5. The method of claim 4 , wherein the low temperature oxide layer has a thickness of 10˜50 Å.
6. The method of claim 3 , wherein removing the resin further comprises using the photoresist pattern as a mask in an etching process that uses O 2 gas.
7. The method of claim 4 , wherein the low temperature oxide layer is formed on or over each floating gate, each patterned first polysilicon gate, and/or the gate oxide.
8. The method of claim 1 , wherein forming the ONO layer comprises sequentially stacking a tunnel oxide layer, a trap nitride layer, and a block oxide layer.
9. The method of claim 8 , wherein the tunnel oxide layer comprises a thermal silicon dioxide layer.
10. The method of claim 9 , wherein the trap nitride layer comprises a silicon nitride layer, and forming the block oxide layer comprises chemical vapor depositing a silicon dioxide layer.
11. The method of claim 4 , further comprising forming the polysilicon sidewall spacers on and/or over the low temperature oxide layer.