User selectable banks for DRAM
View Patent ↗A memory device includes a configurable array of memory cells. A number of array banks is configured based upon data stored in a mode register or decoded by logic circuitry. The memory device remains a full capacity memory, regardless of the number of array banks. Memory address decoding circuitry is adjusted to route address signals to or from a bank address decoder based upon the number of array banks selected.
1. A method of operating a memory, comprising:
supplying a program state of a mode register coupled to address circuitry of a memory array;
configuring the memory array into one of a plurality of bank configurations by the address circuitry routing a selected one of a plurality of address signal input connections to either a row address decoder or a bank address decoder in response to the program state of the mode register.
2. The method of claim 1 , wherein supplying is performed by an external input signal providing the program state to a decode circuit coupled to the address circuitry.
3. The method of claim 1 , further comprising:
configuring the memory array into either four banks or eight banks depending upon the supplied program state.
4. The method of claim 1 , wherein the memory array has X memory cells, and further comprising:
configuring the memory array into either as Y banks each having X/Y memory cells or as Z banks each having X/Z memory cells.
5. A memory device, comprising:
an array of memory cells;
a row address decoder;
a bank address decoder;
a configuration circuit comprising a plurality of address signal input connections and a mode register; and
address circuitry coupled to the configuration circuit to configure the array into one of a plurality of addressable bank configurations by routing a selected one of the plurality of address signal input connections to either the row address decoder or a bank address decoder in response to a program state of the mode register.
6. The memory device of claim 5 , wherein the configuration circuit comprises:
a decode circuit to decode an input signal, the input signal containing data to configure the array of memory cells.
7. The memory device of claim 5 , wherein the address circuitry is further configured to define, in response to the program state, the array into one of the plurality of bank configurations.
8. The memory device of claim 7 , wherein the address circuitry is further configured to define the array into a configuration of four or eight memory banks.
9. The memory device of claim 7 , wherein the array has X memory cells and wherein the address circuitry is further configured to define the array into Y banks each having X/Y memory cells or into Z banks each having X/Z memory cells.
10. The memory device of claim 7 , wherein the array has X rows, Y columns, and Z banks, wherein the array comprises X*Y*Z memory cells.
11. A method of configuring a memory device, comprising:
programming a mode register with a program state indicating a bank configuration, wherein the mode register is coupled to address circuitry of a memory array;
supplying a configuration signal based on the program state of the mode register;
configuring an array of memory cells of the memory device into one of a plurality of addressable bank configurations, each of the plurality of addressable bank configurations having a different number of banks; and
selecting the one of the plurality of addressable bank configurations by routing a selected one of a plurality of address signal input connections to either a row address decoder or a bank address decoder in response to the configuration signal.
12. The method of claim 11 , further comprising:
providing the configuration signal from a decode circuit connectable to an external input signal indicating the bank configuration.
13. The method of claim 11 , wherein the array of memory cells is configured into either four banks or eight banks.
14. The method of claim 13 , wherein the address circuitry is further configured to route to the bank address decoder for an eight bank configuration and to the row address decoder for a four bank configuration.
15. The method of claim 11 , wherein the array of memory cells has X memory cells, and is configured into Y banks each having X/Y memory cells or Z banks each having X/Z memory cells.