Memory cell array
View Patent ↗Disclosed is a memory cell array including: word lines and first and second bit lines respectively connected to memory cells, wherein each memory cell includes a MOS transistor and a switching element formed inside a contact hole, the switching element includes first and second conductive layers and a gap in which a resistance value is changed by applying a predetermined voltage, each word line is connected to a gate electrode, each first bit line is connected to a second electrode, each second bit line is connected to the second conductive layer, and data is written by supplying a write voltage to the first bit line connected to the selected memory cell and specifying the word line connected to the memory cell, and data is read by supplying a read voltage to the first bit lines connected to the memory cell and specifying the word line connected to the memory cells.
1. A memory cell array in which a plurality of memory cells are arranged in an array, the memory cell array comprising:
a plurality of word lines respectively connected to the plurality of memory cells;
a plurality of first bit lines respectively connected to the plurality of memory cells; and
a plurality of second bit lines respectively connected to the plurality of memory cells,
wherein each of the memory cells includes:
a metal-oxide semiconductor (MOS) transistor; and
a switching element which is formed inside a contact hole including a first electrode connected to a first diffusion layer of the MOS transistor,
wherein the switching element includes:
a first conductive layer;
a second conductive layer provided above the first conductive layer; and
a gap having a size of nanometer order which is formed between the first conductive layer and the second conductive layer, and in which gap a phenomenon that a resistance value is changed by application of a predetermined voltage between the first conductive layer and the second conductive layer occurs,
wherein each of the word lines is connected to a gate electrode of the MOS transistor,
wherein each of the first bit lines is connected to a second electrode connected to a second diffusion layer of the MOS transistor,
wherein each of the second bit lines is connected to the second conductive layer, and
wherein data is written in one or more selected memory cells among the memory cells by supplying a write voltage to one or more of the first bit lines connected to the one or more selected memory cells and specifying one or more of the word lines connected to the one or more selected memory cells, and data is read from one or more selected memory cells among the memory cells by supplying a read voltage to one or more of the first bit lines connected to the one or more selected memory cells and specifying one or more of the word lines connected to the one or more selected memory cells.
2. The memory cell array according to claim 1 ,
wherein the first bit lines are respectively connected to voltage sense amplifiers, and
wherein the second bit lines are connected to a ground.
3. The memory cell array according to claim 1 ,
wherein the second bit lines are connected to a ground when the write voltage is supplied to the one or more first bit lines, and the second bit lines are connected to a current sense amplifier when the read voltage is supplied to the one or more first bit lines.
4. The memory cell array according to claim 3 ,
wherein at least two second bit lines among the plurality of second bit lines join each other, and
wherein the joined second bit lines are connected to the ground through a ground terminal when the write voltage is supplied to the one or more first bit lines, and the joined second bit lines are connected to the current sense amplifier when the read voltage is supplied to the one or more first bit lines.