Gate driving device and liquid crystal display having the same

1. A gate driving device comprising:

a plurality of stages;

a first dummy stage connected to the plurality of stages; and

a second dummy stage connected to the first dummy stage,

wherein

stages of the plurality of stages are cascaded,

the first dummy stage comprises:

a first charge unit which receives a first input signal from a previous stage of the plurality of stages and is thereby charged; and

a first pull-up transistor which outputs a clock signal when the first charge unit reaches a first charge level, and

the second dummy stage comprises:

a second charge unit which receives a second input signal from the first dummy stage and is thereby charged; and

a second pull-up transistor which outputs the clock signal when the second charge unit reaches a second charge level,

wherein a channel width of the second pull-up transistor is greater than a channel width of the first pull-up transistor.

2. The gate driving device of claim 1 , wherein each stage of the plurality of stages includes a third charge unit which receives a third input signal from a previous stage of said each stage of the plurality of stages and is thereby charged, and a third pull-up transistor which outputs the clock signal when the third charge unit reaches the first charge level.

3. The gate driving device of claim 2 , wherein

each stage of the plurality of stages includes a first capacitor which receives the third input signal and is thereby charged, and a first carry signal generating transistor which outputs the clock signal as a first carry signal when the first capacitor reaches a third charge level, and

the first dummy stage includes a second capacitor which receives the first input signal and is thereby charged, and a second carry signal generating transistor which outputs the clock signal as a second carry signal, wherein the second carry signal generating transistor is controlled by the second capacitor.

4. The gate driving device of claim 3 , wherein a channel width of the second pull-up transistor is determined by a value obtained by multiplying a total parasitic capacitance generated by a gate signal outputted from the second dummy stage with a ratio of a channel width of the third pull-up transistor to a parasitic capacitance of a gate line connected to the third pull-up transistor.

5. The gate driving device of claim 2 , wherein

the first dummy stage includes a first buffer transistor which transmits the first input signal to the first charge unit,

the second dummy stage includes a second buffer transistor which transmits the second input signal to the second charge unit, and

a channel width of the second buffer transistor is greater than a channel width of the first buffer transistor.

6. The gate driving device of claim 1 , wherein the second dummy stage outputs a gate signal to the plurality of stages and the first dummy stage to initialize the plurality of stages and the first dummy stage.

7. A liquid crystal display comprising:

a liquid crystal panel including gate lines; and

a gate driving device including a plurality of stages, a first dummy stage connected to the plurality of stages and a second dummy stage connected to the first dummy stage,

wherein

stages of the plurality of stages are cascaded,

the first dummy stage comprises:

a first charge unit which receives a first input signal from a previous stage of the plurality of stages and is thereby charged; and

a first pull-up transistor which outputs a clock signal when the first charge unit reaches a first charge level, and

the second dummy stage comprises:

a second charge unit which receives a second input signal from the first dummy stage and is thereby charged; and

a second pull-up transistor which outputs the clock signal when the second charge unit reaches a second charge level,

wherein a channel width of the second pull-up transistor is greater than a channel width of the first pull-up transistor.

8. The liquid crystal display of claim 7 , wherein each of the plurality of stages includes a third charge unit which receives a third input signal from a previous stage of the plurality of stages and is thereby charged, and a third pull-up transistor which outputs the clock signal when the third charge unit reaches the first charge level.

9. The liquid crystal display of claim 8 , wherein

each stage of the plurality of stages includes a first capacitor which receives the third input signal and is thereby charged, and a first carry signal generating transistor which outputs the clock signal as a first carry signal when the first capacitor reaches a third charge level, and

the first dummy stage includes a second capacitor which receives the first input signal and is thereby charged, and a second carry signal generating transistor which outputs the clock signal as a second carry signal when the second capacitor reaches a fourth charge level higher than the third charge level.

10. The liquid crystal display of claim 9 , wherein a width of the second pull-up transistor is determined by a value obtained by multiplying a total parasitic capacitance generated by a gate signal outputted from the second dummy stage with a ratio of a channel width of the third pull-up transistor to a parasitic capacitance of a gate line connected to the third pull-up transistor.

11. The liquid crystal display of claim 9 , wherein

the second charge level of the second pull-up transistor is determined by the total parasitic capacitance generated by the gate signal outputted from the second dummy stage, and

the first charge level of the first pull-up transistor is determined by the second charge level of the second pull-up transistor.

12. The liquid crystal display of claim 8 , wherein

the first dummy stage includes a first buffer transistor which transmits the first input signal to the first charge unit,

the second dummy stage includes a second buffer transistor which transmits the second input signal to the second charge unit, and

a channel width of the second buffer transistor is greater width than a channel width of the first buffer transistor.

13. The liquid crystal display of claim 7 , wherein the second dummy stage outputs the gate signal to the plurality of stages and the first dummy stage to initialize the plurality of stages and the first dummy stage.

14. The liquid crystal display of claim 13 , further comprising a third dummy stage and a fourth dummy stage, wherein

the plurality of stages are divided into a first group and a second group,

the first group is connected to the first dummy stage and the second dummy stage,

the second group is connected to the third dummy stage and the fourth dummy stage,

the third dummy stage includes a fourth charge unit which receives a fourth input unit from a previous stage of the second group and is thereby charged, and a fourth pull-up transistor which outputs a second clock signal when the fourth charge unit reaches the first charge level,

the fourth dummy stage includes a fifth charge unit which receives a fifth input unit from the third dummy stage and is thereby charged, and a fifth pull-up transistor which outputs the second clock signal when the fifth charge unit reaches a second charge level higher than the first charge level, and

the first clock signal and the second clock signal are different from each other.

15. The liquid crystal display of claim 14 , wherein the fourth dummy stage outputs a gate signal to the second group and the third dummy stage to initialize the second group and the third dummy stage.

16. A liquid crystal display comprising:

a liquid crystal panel including gate lines; and

a gate driving device including a plurality of stages, a first dummy stage connected to the plurality of stages and a second dummy stage connected to the first dummy stage,

wherein

stages of the plurality of stages are cascaded,

the stages are connected to gate lines to sequentially supply gate signals thereto

the first dummy stage comprises:

a first charge unit which receives a first input signal from a previous stage of the plurality of stages and is thereby charged; and

a first pull-up transistor which has a first channel width, and the second dummy stage comprises:

a second charge unit which receives a second input signal from the first dummy stage and is thereby charged; and

a second pull-up transistor which has a second channel width greater than the first channel width.

17. The liquid crystal display of claim 16 , wherein

the first pull-up transistor outputs a first clock signal when the first charge unit reaches a first charge level, and

the second pull-up transistor outputs the first clock signal when the second charge unit reaches a second charge level higher than the first charge level.

18. The liquid crystal display of claim 16 , wherein

the first dummy stage includes a first buffer transistor which transmits the first input signal to the first charge unit,

the second dummy stage includes a second buffer transistor which transmits the second input signal to the second charge unit, and

a channel width of the second buffer transistor is greater than a channel width of the first buffer transistor.