Method for dicing a semiconductor wafer, a chip diced from a semiconductor wafer, and an array of chips diced from a semiconductor wafer
View Patent ↗A method for dicing a semiconductor wafer, including: cutting a reference slot in a back main surface of the wafer; cutting a back slot in the back main surface, the back slot positioned with respect to the reference slot; determining a desired location for a chip edge with respect to the reference slot; and applying radiant energy in a path such that a series of reformed regions are formed within the wafer along the path. A crystalline structure of the wafer is modified in the series of reformed regions and an alignment of an edge of the laser is with respect to the desired location for the chip edge and in alignment with the back slot. The method includes separating the wafer along the series of reformed regions to divide portions of the wafer on either side of the series of reformed regions.
1. A method for dicing a semiconductor wafer, comprising:
cutting a reference slot in a back main surface of the wafer;
cutting a back slot in the back main surface of the wafer, the back slot positioned with respect to the reference slot;
determining a desired location for a first chip edge with respect to the reference slot;
applying, using a radiant energy source, radiant energy in a first path such that a first series of reformed regions are formed within the wafer along the first path, wherein:
a crystalline structure of the wafer is modified in the first series of reformed regions; and,
a location of a first edge of the radiant energy source is:
with respect to the desired location for the first chip edge; and,
in alignment with the back slot; and,
separating the wafer along the first series of reformed regions to divide portions of the wafer on either side of the first series of reformed regions.
2. The method of claim 1 wherein applying radiant energy includes applying a laser.
3. The method of claim 1 , further comprising:
applying radiant energy in a second path such that a second series of reformed regions are formed within the wafer along the second path, wherein:
the crystalline structure of the wafer is modified in the second series of reformed regions; and,
an alignment of a second edge of the laser is:
with respect to the desired location for the second chip edge; and,
in alignment with the back slot; and,
separating the wafer along the second series of reformed regions to divide portions of the wafer on either side of the second series of reformed regions.
4. The method of claim 3 wherein the back slot has a first width and the first and second paths are separated by a second width less than the first width.
5. The method of claim 3 wherein a region of the wafer between the first and second series of reformed regions includes at least one feature used in the fabrication of the wafer.
6. The method of claim 1 wherein determining the desired location for a first chip edge with respect to the reference slot includes aligning the first edge with the desired location for the first chip edge.
7. The method of claim 1 wherein:
the back slot includes a slot surface substantially parallel to the front main surface;
the wafer has a thickness between the front main surface and the slot surface; and,
wherein determining a desired location for a first chip edge with respect to the reference slot includes positioning the first edge according to the thickness.
8. The method of claim 7 wherein positioning the first edge according to the thickness includes:
positioning the first edge at a first distance from the desired location for the first chip edge for a thickness having a first value; and,
positioning the first edge at a second distance, greater than the first distance, from the desired location for the first chip edge for a thickness having a second value greater than the first value.
9. The method of claim 1 wherein applying radiant energy in the first path such that the first series of reformed regions are formed within the wafer includes forming the first series of reformed regions substantially orthogonal to a front main surface of the wafer.
10. The method of claim 1 wherein applying radiant energy in the first path such that the first series of reformed regions are formed within the wafer includes forming the first series of reformed regions at an acute angle with respect to the front main surface of the wafer.
11. The method of claim 1 wherein separating the wafer along the first series of reformed regions includes:
forming an end surface on the die between the front and back main surfaces; and,
forming a substantially square corner between the front main surface and at least a portion of the end surface on the die.
12. The method of claim 1 wherein the position of the first edge of the laser with respect to the desired location for the first chip edge includes a position of the first edge at a first distance from the desired location for the first chip edge; and,
the method further comprising applying radiant energy in a second path such that a second series of reformed regions are formed within the wafer along the second path, a position of the first edge of the laser at a second distance, less than the first distance, from the desired location for the first chip edge.
13. A method for dicing a semiconductor wafer, comprising:
cutting a reference slot in a back main surface of the wafer;
cutting a back slot in the back main surface of the wafer, the back slot positioned with respect to the reference slot;
determining a desired location for a first chip edge with respect to the reference slot;
applying, using a radiant energy source, radiant energy in a first path such that a first series of reformed regions are formed within the wafer along the first path, wherein:
a crystalline structure of the wafer is modified in the first series of reformed regions; and,
an alignment of a first edge of the radiant energy source is:
with respect to the desired location for the first chip edge; and,
in alignment with the back slot;
determining a desired location for a second chip edge with respect to the reference slot;
applying radiant energy in a second path such that a second series of reformed regions are formed within the wafer along the second path, wherein:
the crystalline structure of the wafer is modified in the second series of reformed regions; and,
an alignment of a second edge of the laser is:
with respect to the desired location for the second chip edge; and,
in alignment with the back slot; and,
separating the wafer along the first and second series of reformed regions to divide portions of the wafer on either side of the first and second series of reformed regions.
14. A method for dicing a semiconductor wafer, comprising:
cutting a reference slot in a back main surface of the wafer;
cutting a back slot in the back main surface of the wafer, the back slot positioned with respect to the reference slot;
determining a desired location for a chip edge with respect to the reference slot;
applying, using a radiant energy source, radiant energy in a path such that a series of reformed regions are formed within the wafer along the path, wherein:
a crystalline structure of the wafer is modified in the reformed regions; and,
an alignment of an edge of the radiant energy source is with respect to the desired location for the chip edge; and,
separating the wafer along the series of reformed regions to divide portions of the wafer on either side of the series of reformed regions, wherein applying radiant energy in the first path such that the first series of reformed regions are formed within the wafer includes forming the first series of reformed regions at an acute angle with respect to the front main surface of the wafer.