Method and apparatus to improve the ability to decode ADS-B squitters through multiple processing paths
View Patent ↗A system is delineated comprising a TCAS receiver having one or more filters, one or more amplifiers and one or more A/D converters, the one or more A/D converters for digitizing analog data into digital data for decoding one or more of an ADS-B message and a TIS-B message; and circuitry for receiving the digital data and decoding the one or more of an ADS-B message and a TIS-B message, wherein the circuitry includes two or more paths for the decoding.
1. A system, comprising:
a TCAS receiver with at least A3 receiver sensitivity for receiving and decoding one or more of an ADS-B message and a TIS-B message, said at least A3 receiver sensitivity achieved without an active antenna; and
a passive antenna coupled to the TCAS receiver.
2. A system, comprising:
a TCAS receiver having one or more filters, one or more amplifiers and one or more A/D converters, the one or more A/D converters for digitizing analog data into digital data for decoding one or more of an ADS-B message and a TIS-B message; and
circuitry for receiving the digital data and decoding the one or more of an ADS-B message and a TIS-B message, wherein the circuitry includes two or more paths for the decoding.
3. The system of claim 2 wherein the circuitry comprises one or more of an ASIC, an FPGA and a DSP.
4. The system of claim 2 further comprising a processor for receiving the decoded messages from the circuitry.
5. The system of claim 2 further including, before the circuitry for receiving the digital data, circuitry for determining a preamble reference level for one or more of an ADS-B message and a TIS-B message.
6. The system of claim 5 wherein one or more of the two decoding paths employs a plurality of offsets to adjust the determined preamble reference level.
7. The system of claim 2 wherein the two or more paths perform different processes on the digital data for decoding.
8. A method, comprising:
providing a TCAS receiver having one or more filters, one or more amplifiers and one or more A/D converters, the one or more A/D converters for digitizing analog data into digital data for decoding one or more of an ADS-B message and a TIS-B message; and
receiving the digital data and decoding the one or more of an ADS-B message and a TIS-B message with circuitry including two or more paths for the decoding.
9. The method of claim 8 wherein the circuitry comprises one or more of an ASIC, an FPGA and a DSP.
10. The method of claim 8 further comprising receiving the decoded messages from the circuitry.
11. The method of claim 8 further including determining a preamble reference level for one or more of an ADS-B message and a TIS-B message.
12. The method of claim 11 wherein one or more of the two decoding paths employs a plurality of offsets to adjust the determined preamble reference level.
13. The method of claim 8 wherein the two or more paths perform different processes on the digital data for decoding.