Thin film transistor array panel and liquid crystal display including the panel

1. A thin film transistor array panel comprising:

substrate;

a gate line disposed on the substrate and extending in a first direction;

a capacitive electrode separated from the gate line and elongated in a second direction;

a data line intersecting the gate line;

a thin film transistor connected to the gate line and the data line and including a drain electrode;

a coupling electrode overlapping the capacitive electrode and connected to the drain electrode; and

a pixel electrode including at least one first subpixel electrode connected to the drain electrode and a second subpixel electrode connected to the capacitive electrode and spaced apart from the at least one first subpixel electrode by a gap that overlaps the capacitive electrode or a coupling electrode.

2. A liquid crystal display comprising:

a gate line;

a data line intersecting the gate line;

a capacitive electrode separated from the gate line and elongated substantially parallel to the date line;

a thin film transistor connected to the gate line and the data line and including a drain electrode;

a coupling electrode overlapping the capacitive electrode and connected to the drain electrode;

a pixel electrode including a first subpixel electrode connected to the drain electrode and a second subpixel electrode connected to the capacitive electrode and spaced apart from the first subpixel electrode by a gap that overlaps the capacitive electrode or the coupling electrode;

a common electrode disposed opposite the pixel electrode; and

a liquid crystal layer interposed between the pixel electrode and the common electrode.

3. A method of manufacturing thin film transistor array panel, the method comprising:

forming a gate line and a capacitive electrode on a substrate, the gate line and the capacitive electrode separated from each other and extending in different directions;

forming a data line including a source electrode, a drain electrode separated from the date line, and a coupling electrode overlapping the capacitive electrode and connected to the drain electrode; and

forming a pixel electrode including at least one first subpixel electrode connected to the drain electrode and a second subpixel electrode connected to the capacitive electrode,

wherein the second subpixel electrode is spaced apart from the at least one first subpixel electrode by a gap that overlaps the capacitive electrode or the coupling electrode.