Receiver for clock reconstitution
View Patent ↗A receiver for clock reconstitution in a semiconductor field includes a termination resistor arranged between two input stages, to which a pair of input signals are input, the termination resistor including a first resistor and a second resistor; a strobe signal generator for generating a strobe signal, using a first signal corresponding to a differential voltage output from a node between the first resistor and the second resistor; and a clock reconstitutor for generating a clock signal in response to the strobe signal generated from the strobe signal generator.
1. An apparatus comprising:
a termination resistor arranged between two input stages, to which a pair of input signals are input, the termination resistor comprising a first resistor and a second resistor;
a strobe signal generator configured to generate a strobe signal, using a first signal corresponding to a differential voltage output from a node between the first resistor and the second resistor; and
a clock reconstitutor configured to generate a clock signal in response to the strobe signal generated from the strobe signal generator.
2. The apparatus of claim 1 , wherein the strobe signal generator comprises:
a low-frequency filter configured to filter the first signal, thereby outputting a second signal having a lower voltage level than the first signal; and
a fast-transition detector configured to receive the first signal and the second signal, thereby generating the strobe signal.
3. The apparatus of claim 2 , wherein the fast-transition detector generates the strobe signal when a voltage difference is generated between the first signal and the second signal as the first signal is varied at a transition rate above a predetermined minimum.
4. The apparatus of claim 2 , wherein the fast-transition detector does not generate the strobe signal when no voltage difference is generated between the first signal and the second signal as the first signal is varied at a transition rate below a predetermined minimum.
5. The apparatus of claim 1 , wherein a receiver sequentially transmits a dummy signal, a strobe signal, a dummy signal, a clock signal, and a data signal, for signal transmission interface.
6. The apparatus of claim 5 , wherein the receiver detects the clock signal after extraction of the strobe signal, and detects the data signal after the detection of the clock signal.
7. A method comprising:
providing a pair of input signals to a termination resistor arranged between two input stages, the termination resistor comprising a first resistor and a second resistor;
generating a strobe signal using a first signal corresponding to a differential voltage output from a node between the first resistor and the second resistor; and
generating a reconstituted clock signal in response to the strobe signal.
8. The method of claim 7 , generating the strobe signal includes:
low-frequency filtering the first signal, thereby outputting a second signal having a lower voltage level than the first signal; and
receiving the first signal and the second signal, wherein generating the strobe signal is based on a transition detection of the first signal and second signal.
9. The method of claim 8 , wherein the strobe signal is generated when a voltage difference is generated between the first signal and the second signal as the first signal is varied at a rate above a predetermined minimum.
10. The method of claim 8 , wherein strobe signal is not generated when no voltage difference is generated between the first signal and the second signal as the first signal is varied at a transition rate below a predetermined minimum.
11. The method of claim 7 , wherein a receiver sequentially transmits a dummy signal, a strobe signal, a dummy signal, a clock signal, and a data signal, for signal transmission interface.
12. The method of claim 11 , wherein the receiver detects the clock signal after extraction of the strobe signal, and detects the data signal after the detection of the clock signal.
13. A receiver for clock reconstitution comprising:
a termination resistor arranged between two input stages, to which a pair of input signals are input, the termination resistor comprising a first resistor and a second resistor;
a strobe signal generator configured to generate a strobe signal, using a first signal corresponding to a differential voltage output from a node between the first resistor and the second resistor; and
a clock reconstitutor configured to generate a clock signal in response to the strobe signal generated from the strobe signal generator.
14. The receiver of claim 13 , wherein the strobe signal generator comprises:
a low-frequency filter for filtering the first signal, thereby outputting a second signal having a lower voltage level than the first signal; and
a fast-transition detector for receiving the first signal and the second signal, thereby generating the strobe signal.
15. The receiver of claim 14 , wherein the fast-transition detector generates the strobe signal when a voltage difference is generated between the first signal and the second signal as the first signal is varied at a fast transition rate.
16. The receiver of claim 14 , wherein the fast-transition detector does not generate the strobe signal when no voltage difference is generated between the first signal and the second signal as the first signal is varied at a slow transition rate.
17. The receiver of claim 14 , wherein the receiver sequentially transmits a dummy signal, a strobe signal, a dummy signal, a clock signal, and a data signal, for signal transmission interface.
18. The receiver of claim 17 , wherein the receiver detects the clock signal after extraction of the strobe signal, and detects the data signal after the detection of the clock signal.
19. The receiver of claim 13 , wherein the receiver sequentially transmits a dummy signal, a strobe signal, a dummy signal, a clock signal, and a data signal, for signal transmission interface.
20. The receiver of claim 19 , wherein the receiver detects the clock signal after extraction of the strobe signal, and detects the data signal after the detection of the clock signal.