Operational amplifier
View Patent ↗An operational amplifier capable of suppressing power consumption and noise generation includes an offset modifier including a differential amplification circuit, and an offset memory for storing an offset voltage using a latch circuit. The differential amplification circuit includes first and second NMOS transistors connected to an input terminal, first and second PMOS transistors respectively connected to drains of the first and second NMOS transistors, a third NMOS transistor connected to sources of the first and second NMOS transistors, a third PMOS transistor connected to a source of the second PMOS transistor, a fourth NMOS transistor connected to the third PMOS transistor, to form an output to be applied to the offset memory, and left and right modification blocks each connected to an associated one of the first and second NMOS transistor in parallel.
1. An apparatus comprising:
an offset modifier including a differential amplification circuit; and
an offset memory configured to store an offset voltage using a latch circuit,
wherein the differential amplification circuit includes:
first and second NMOS transistors connected to an input terminal,
first and second PMOS transistors respectively connected to drains of the first and second NMOS transistors,
a third NMOS transistor connected to sources of the first and second NMOS transistors,
a third PMOS transistor connected to a drain of the second PMOS transistor and a source of the second PMOS transistor,
a fourth NMOS transistor connected to the third PMOS transistor to form an output to be applied to the offset memory, and
left and right modification blocks each connected to an associated one of the first and second NMOS transistor in parallel.
2. The apparatus of claim 1 , wherein the left modification block comprises a plurality of NMOS transistors connected in parallel.
3. The apparatus of claim 2 , wherein the left modification block comprises a plurality of switches connected in parallel.
4. The apparatus of claim 3 , wherein each of the plural NMOS transistors is connected in series with an associated one of the plurality of switches.
5. The apparatus of claim 1 , wherein the right modification block comprises a plurality of NMOS transistors connected in parallel.
6. The apparatus of claim 5 , wherein the right modification block comprises a plurality of switches connected in parallel.
7. The apparatus of claim 6 , wherein each of the plural NMOS transistors is connected in series with an associated one of the switches.
8. The apparatus of claim 1 , wherein the first NMOS transistor is connected to gates of the plural NMOS transistors of the left modification block at a gate of the first NMOS transistor.
9. The apparatus of claim 8 , wherein the source of the first NMOS transistor is connected to a drain of the third NMOS transistor.
10. The apparatus of claim 9 , wherein the drain of the first NMOS transistor is connected to a gate of the first PMOS transistor and to a drain of the first PMOS transistor.
11. The apparatus of claim 10 , wherein the second NMOS transistor is connected to gates of the plural NMOS transistors of the right modification block at a gate of the second NMOS transistor.
12. The apparatus of claim 11 , wherein the source of the second NMOS transistor is connected to the drain of the third NMOS transistor.
13. The apparatus of claim 12 , wherein the drain of the second NMOS transistor is connected to the drain of the second PMOS transistor.
14. The apparatus of claim 1 , wherein a source of the first PMOS transistor is connected to a source of the second PMOS transistor and a source of the third PMOS transistor.
15. The apparatus of claim 14 , wherein the gate of the second PMOS transistor is connected to the gate of the first PMOS transistor.
16. The apparatus of claim 15 , wherein the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor.
17. The apparatus of claim 1 , wherein a bias voltage is supplied to a gate of the third NMOS transistor so that the third NMOS transistor functions as a current source.
18. An apparatus comprising:
a VCOM driver including a plurality of operational amplifiers comprising an offset modifier including a differential amplification circuit and an offset memory configured to store an offset voltage using a latch circuit, the differential amplification circuit including:
first and second NMOS transistors connected to an input terminal,
first and second PMOS transistors respectively connected to drains of the first and second NMOS transistors,
a third NMOS transistor connected to sources of the first and second NMOS transistors,
a third PMOS transistor connected to a drain of the second PMOS transistor and a source of the second PMOS transistor,
a fourth NMOS transistor connected to the third PMOS transistor to form an output to be applied to the offset memory, and
left and right modification blocks each connected to an associated one of the first and second NMOS transistor in parallel,
wherein the operational amplifiers are connected while having inverting input terminals respectively connected to input terminals, and non-inverting input terminals respectively connected to an output terminal via first and second switches.
19. An apparatus comprising:
non-inverting amplifier including an operational amplifier including an offset modifier having a differential amplification circuit and an offset memory configured to store an offset voltage using a latch circuit, the differential amplification circuit including:
first and second NMOS transistors connected to an input terminal,
first and second PMOS transistors respectively connected to drains of the first and second NMOS transistors,
a third NMOS transistor connected to sources of the first and second NMOS transistors,
a third PMOS transistor connected to a source of the second PMOS transistor,
a fourth NMOS transistor connected to the third PMOS transistor to form an output to be applied to the offset memory, and
left and right modification blocks each connected to an associated one of the first and second NMOS transistor in parallel,
wherein the operational amplifier having an inverting input terminal connected to an input terminal, a non-inverting input terminal connected to a node between first and second resistors connected in series, and an output terminal connected to one end of the second resistor.