Liquid crystal display with reduced image flicker and driving method thereof

1. A liquid crystal display device comprising:

a gate driver for outputting a first gate driving signal and a second gate driving signal according to a first clock signal or a second clock signal, the gate driver comprising:

a first output end for outputting the first gate driving signal; and

a second output end for outputting the second gate driving signal;

a control circuit configured to:

provide a third clock signal and a fourth clock signal, wherein the third and fourth clock signals periodically switch polarities and have opposite polarities at the same time; and

provide a charge sharing signal according to parasitic capacitances at the first and second output ends of the gate driver, the charge-sharing signal including:

a first disable period corresponding to an output period of the first output end; and

a second disable period corresponding to an output period of the second output end;

wherein the parasitic capacitance at the second output end is larger than the parasitic capacitance at the first output end, and the first disable period is longer than the second disable period; and

a charge-sharing circuit configured to:

generate the first clock signal by performing charge-sharing on the third and fourth clock signals during the first disable period; and

generate the second clock signal by performing charge-sharing on the third and fourth clock signals during the second disable period;

wherein the first clock signal includes a signal falling edge which descends from a high voltage level to a first voltage level, and the second clock signal includes a signal falling edge which descends from the high voltage level to a second voltage level.

2. The liquid crystal display device of claim 1 , wherein a transmission path between the charge-sharing circuit and the second output end of the gate driver is longer than a transmission path between the charge-sharing circuit and the first output end of the gate driver, and the second voltage level is higher than the first voltage level.

3. The liquid crystal display device of claim 1 , wherein the second voltage level is higher than the first voltage level.

4. The liquid crystal display device of claim 1 , wherein the charge-sharing circuit comprises a level shifter for enlarging the third and fourth clock signals.

5. The liquid crystal display device of claim 1 , wherein the charge-sharing circuit comprises:

a first output end for outputting the first clock signal;

a second output end for outputting the second clock signal; and

a resistor coupled between the first and second output ends of the charge-sharing circuit.

6. The liquid crystal display device of claim 1 , wherein the gate driver is fabricated using GOA (gate driver on array) technique.

7. The liquid crystal display device of claim 1 , wherein the gate driver comprises:

a first shift register unit for supplying the first gate driving signal by outputting the first clock signal; and

a second shift register unit for supplying the second gate driving signal by outputting the second clock signal.

8. The liquid crystal display device of claim 7 , wherein the first shift register unit outputs the first gate driving signal using a first thin film transistor (TFT) switch, and the second shift register unit outputs the second gate driving signal using a second TFT switch, and wherein the parasitic capacitance at the first output end of the gate driver is related to a parasitic capacitance contributed by the first TFT switch, and the parasitic capacitance at the second output end of the gate driver is related to a parasitic capacitance contributed by the first and second TFT switches.

9. The liquid crystal display device of claim 1 , wherein the control circuit is an application-specific integrated circuit (ASIC).

10. A method for driving a liquid crystal display device comprising:

providing a first clock signal and a second clock signal, wherein the first and second clock signals periodically switch polarities and have opposite polarities at the same time;

providing a charge-sharing signal including a first disable period corresponding to an output period of the first output end and a second disable period corresponding to an output period of the second output end, wherein the parasitic capacitance at the second output end is larger than the parasitic capacitance at the first output end, and the first disable period is longer than the second disable period;

providing a third clock signal by performing charge-sharing on the first and second clock signals during the first disable period, wherein the third clock signal includes a signal falling edge which descends from a high voltage level to a first voltage level; and

providing a fourth clock signal by performing charge-sharing on the first and second clock signals during the second disable period, wherein the fourth clock signal includes a signal falling edge which descends from the high voltage level to a second voltage level.

11. The method of claim 10 further comprising enhancing voltage levels of the first and second clock signals before performing charge-sharing.

12. The method of claim 10 wherein the first and second clock signals perform charge-sharing using a resistor.

13. The method of claim 10 further comprising:

outputting the third clock signal at the first output end during the first disable period; and

outputting the fourth clock signal at the second output end during the second disable period.