Field effect transistor having graphene channel layer
View Patent ↗Provided is a field effect transistor including a graphene channel layer, and capable of increasing an on/off ratio of an operating current by using the graphene of the graphene channel layer. The field effect transistor includes: a substrate; the graphene channel layer which is disposed on a portion of the substrate and includes graphene; a first electrode disposed on a first region of the graphene channel layer and a portion of the substrate; an interlayer disposed on a second region of the graphene channel layer, which is apart from the first region, and a portion of the substrate; a second electrode disposed on the interlayer; a gate insulation layer disposed on a portion of the graphene channel layer, the first electrode, and the second electrode; and a gate electrode disposed on a portion of the gate insulation layer.
1. A field effect transistor, comprising:
a substrate;
a graphene channel layer which is disposed on a portion of the substrate and comprises graphene;
a first electrode disposed on a first region of the graphene channel layer and on a portion of the substrate;
an interlayer disposed on a second region of the graphene channel layer, which is spaced apart from the first region, and on a portion of the substrate;
a second electrode disposed on the interlayer;
a gate insulation layer disposed on a portion of the graphene channel layer, the first electrode, and the second electrode; and
a gate electrode disposed on a portion of the gate insulation layer,
wherein the interlayer comprises an insulation layer.
2. The field effect transistor of claim 1 , wherein the graphene is semi-metal graphene having no band gap and the level of the Fermi surface changes by a voltage applied to the gate electrode.
3. The field effect transistor of claim 1 , wherein the second electrode overlaps with the graphene channel layer and the interlayer is interposed therebetween.
4. The field effect transistor of claim 1 , wherein the second electrode covers the interlayer either completely or partially.
5. The field effect transistor of claim 1 , wherein a thickness of the interlayer is sufficient to cause a tunnelling effect between the graphene channel layer and the second electrode.
6. The field effect transistor of claim 1 , wherein each of the first electrode and the second electrode is either a source electrode or a drain electrode.
7. A field effect transistor, comprising:
a substrate;
a graphene channel layer which is disposed on a portion of the substrate and comprises graphene;
a first electrode disposed on a first region of the graphene channel layer and on a portion of the substrate;
an interlayer disposed on a second region of the graphene channel layer, which is spaced apart from the first region, and on a portion of the substrate;
a second electrode disposed on a portion of the interlayer;
a gate insulation layer disposed on a portion of the graphene channel layer, the first electrode, the interlayer, and the second electrode; and
a gate electrode disposed on a portion of the gate insulation layer,
wherein the second electrode is spaced apart from the graphene channel layer by an interlayer that is interposed therebetween, and the second electrode and the graphene channel layer do not overlap.
8. The field effect transistor of claim 7 , wherein the graphene is semi-metal graphene having no band gap and the level of the Fermi surface changes by a voltage applied to the gate electrode.
9. The field effect transistor of claim 7 , wherein the interlayer comprises a semiconductor having a band gap of a size with which a field effect occurs due to a voltage applied to the gate electrode.
10. The field effect transistor of claim 7 , wherein a thickness interlayer is sufficient to cause a tunnelling effect between the graphene channel layer and the second electrode.
11. The field effect transistor of claim 7 , wherein the interlayer comprises semiconductor graphene or graphene oxide.
12. The field effect transistor of claim 7 , wherein the interlayer has a first portion and a second portion,
wherein the first portion of the interlayer is interposed between the first electrode and the graphene channel layer,
wherein the second portion of the interlayer is interposed between the second electrode and the graphene channel layer.