Semiconductor integrated circuit device
View Patent ↗Interconnections are formed over an interlayer insulating film which covers MISFETQ 1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.
1. A semiconductor device comprising:
a semiconductor substrate having a scribe region;
an active element formed in the semiconductor substrate;
a plurality of dummy wirings arranged in the scribe region and not connected to the active element; and
a marker formed in the scribe region and used for adjusting a mask of photolithography patterns,
wherein the dummy wirings are the same shape and are regularly arranged, respectively,
wherein a distance between the marker and one of the dummy wirings which is nearest the marker is larger than a distance between each of the dummy wirings, and
wherein the dummy wirings are also arranged in a pad formation region and under a bonding pad.
2. A semiconductor device according to the claim 1 ,
wherein the dummy wirings are also arranged in a peripheral circuit region.
3. A semiconductor device according to the claim 1 ,
wherein the active element is a memory cell of DRAM.
4. A semiconductor device according to the claim 1 ,
wherein the marker and the dummy wirings are arranged at the same layer.
5. A semiconductor device comprising:
a semiconductor substrate having a scribe region;
an active element formed in the semiconductor substrate;
a plurality of dummy wirings arranged in the scribe region and not connected to the active element; and
a marker formed in the scribe region and used for adjusting a mask of photolithography patterns,
wherein the dummy wirings are the same shape and are arranged with the same pitch, respectively,
wherein a distance between the marker and a dummy wiring of the dummy wirings which is nearest the marker is larger than a distance between each of the dummy wirings, and
wherein the dummy wirings are also arranged in a pad formation region and under a bonding pad.
6. A semiconductor device according to the claim 5 ,
wherein the dummy wirings are also arranged in a peripheral circuit region.
7. A semiconductor device according to the claim 5 ,
wherein the active element is a memory cell of DRAM.
8. A semiconductor device according to the claim 5 ,
wherein the marker and the dummy wirings are arranged at the same layer.