Apparatus and method for testing a capacitive transducer and/or associated electronic circuitry

1. An integrated circuit for use in a device having a capacitive transducer, the circuit having a node ( 107 ) for connection to the capacitive transducer (C MEMS ), the integrated circuit comprising;

a capacitor ( 702 ; 108 ) having a first plate and a second plate, the first plate being connected to the node ( 107 );

switching means ( 704 ) coupled to the second plate of the capacitor for selectively coupling a test signal via the capacitor ( 702 ; 108 ) to the node ( 107 ) during a test mode of operation;

circuitry for operating the capacitive transducer in a non-test mode of operation; and

a second capacitor ( 108 ) having a first plate connected to the node ( 107 ) and a second plate connected to a reference voltage,

wherein the switching means is configured to selectively connect the capacitor ( 702 ) in parallel with the second capacitor ( 108 ) during a non-test mode of operation.

2. An integrated circuit as claimed in claim 1 , wherein the switching means ( 704 ) is selectively controlled to connect the second plate of the capacitor ( 702 ; 108 ) to a reference voltage during a non-test mode of operation.

3. An integrated circuit as claimed in claim 1 , wherein the capacitor ( 702 ) has a smaller capacitance than the second capacitor ( 108 ).

4. An integrated circuit as claimed in claim 1 , wherein the capacitor ( 702 ) comprises a plurality of capacitors ( 702 1-N ) and wherein the switching means ( 704 ) comprises a plurality of associated switches ( 704 1-N ), and

wherein the switching means is controlled to selectively connect one or more second plates of the plurality of capacitors ( 702 1-N ) to the test signal during a test mode of operation.

5. An integrated circuit as claimed in claim 4 , wherein at least two of the plurality of capacitors ( 702 1-N ) have different capacitance values.

6. An integrated circuit as claimed in claim 4 , wherein the switching means ( 704 1-N ) is controlled by a control signal derived on-chip, off-chip, or partly on-chip and partly off-chip.

7. An integrated circuit as claimed in claim 1 , wherein the capacitor ( 702 ) comprises a plurality of capacitors ( 702 1-N ), and wherein the switching means ( 704 ) comprises a plurality of associated switches ( 704 1-N ); and

wherein the switching means is controlled to selectively connect one or more second plates of the plurality of capacitors ( 702 1-N ) between a first voltage reference (V 1 ) and a second voltage reference (V 2 ) during a test mode of operation.

8. An integrated circuit as claimed in claim 1 , wherein the test signal is received from a signal source.

9. An integrated circuit as claimed in claim 8 , wherein the signal source is provided on-chip, off-chip, or partly on-chip and off chip.

10. An integrated circuit as claimed in claim 1 , wherein the test signal has a variable amplitude and/or frequency.

11. An integrated circuit as claimed in claim 1 , wherein the node is connected to receive a bias voltage from a voltage source.

12. An integrated circuit as claimed in claim 1 , wherein the capacitive transducer is a MEMS capacitive transducer.

13. A device comprising an integrated circuit as claimed in claim 12 wherein the device is at least one of: an ultrasound imager; a sonar transmitter; a sonar receiver; a mobile phone; a personal desktop assistant; an MP3 player; and a laptop.

14. An integrated circuit as claimed in claim 1 , wherein the node is an output node, and wherein the capacitive transducer is provided on a separate integrated circuit.

15. A method of testing a signal path of an integrated circuit or electronic circuitry coupled to the signal path, the signal path having a capacitor ( 702 ; 108 ) coupled to a node on the signal path, the method comprising:

selectively applying a test signal to the signal path via the capacitor ( 702 ; 108 );

providing a second capacitor ( 108 ) having a first plate connected to the node ( 107 ) and a second plate connected to a reference voltage; and

connecting the capacitor ( 702 ) in parallel with the second capacitor ( 108 ) during a non-test mode of operation.

16. A method as claimed in claim 15 , wherein the node is for connection to the capacitive transducer (C MEMS ), and wherein the capacitor ( 108 ; 702 ) has a first plate connected to the node of the signal path, the method comprising the step of selectively connecting a test signal to a second plate of the capacitor during a test mode of operation.

17. A method as claimed in claim 16 , further comprising the step of selectively connecting the second plate of the capacitor ( 702 ; 108 ) to a reference voltage during a non-test mode of operation.

18. A method as claimed in claim 15 , wherein providing a second capacitor ( 108 ) includes providing the second capacitor ( 108 ) such that the capacitor ( 702 ) has a smaller capacitance than the second capacitor ( 108 ).

19. A method as claimed in claim 15 , further comprising:

providing a plurality of capacitors ( 702 1-N ) in place of the capacitor ( 702 );

providing a switching means ( 704 ) which includes a plurality of associated switches ( 704 1-N ); and

controlling the switching means to selectively connect one or more second plates of the plurality of capacitors ( 702 1-N ) to the test signal during a test mode of operation.

20. A method as claimed in claim 19 , wherein the step of controlling the switching means comprises the step of using a control signal derived on-chip, off-chip, or partly on-chip and partly off-chip.

21. A method as claimed in claim 15 , further comprising:

providing a plurality of capacitors ( 702 1-N ) in place of the capacitor ( 702 );

providing a switching means ( 704 ) which includes a plurality of associated switches ( 704 1-N ); and

controlling the switching means to selectively connect one or more second plates of the plurality of capacitors ( 702 1-N ) between a first voltage reference (V 1 ) and a second voltage reference (V 2 ) during a test mode of operation.

22. A method as claimed in claim 15 , wherein the test signal is received from a signal source provided on-chip, off-chip, or partly on-chip and off-chip.

23. A method as claimed in claim 15 , further comprising the step of varying the frequency and/or amplitude of the test signal during a test mode.

24. A method as claimed in claim 15 , further comprising the step of coupling a voltage source to the node, the voltage source providing a bias voltage to the node.

25. A method as claimed in claim 24 , wherein the test signal is configured to test the operation of the voltage source during a test mode of operation.

26. A method as claimed in claim 15 , further comprising providing a MEMS capacitive transducer which the integrated circuit or electronic circuitry is configured to operate in the non-test mode of operation.

27. A method of testing an assembly comprising a first integrated circuit ( 100 ) comprising a capacitive transducer and a second integrated circuit ( 102 ) comprising associated electronic circuitry, the method comprising the steps of:

mounting the first integrated circuit and the second integrated circuit on a common substrate; and

testing the first and/or second integrated circuit using the method as defined in claim 15 prior to the step of electrically connecting the first integrated circuit and the second integrated circuit.

28. A method as claimed in claim 27 , further comprising the steps of:

packaging the first integrated circuit and the second integrated circuit.

29. A method of testing an assembly comprising a first integrated circuit ( 100 ) comprising a capacitive transducer and a second integrated circuit ( 102 ) comprising associated electronic circuitry, the method comprising the steps of:

mounting the first integrated circuit and the second integrated circuit on a common substrate;

electrically connecting the first integrated circuit and the second integrated circuit; and

testing the first and/or second integrated circuit using the method as defined in claim 15 .

30. A method as claimed in claim 29 , wherein the method comprises the step of testing the continuity of one or more interconnection points between the first integrated circuit and the second integrated circuit.

31. A method as claimed in claim 29 , wherein the method comprises the step of testing the function of the capacitive transducer on the first integrated circuit ( 100 ).

32. A method as claimed in claim 29 , wherein the method comprises the step of testing the function of an amplifier provided on the second integrated circuit.