Control architectures for RF transceivers
View Patent ↗Described herein are devices and methods for implementing a transceiver with independently controlled components. The components may include a programmable digital portion, a dedicated digital portion, and an analog portion. Each independently controlled component includes a programmable controller that resides in the programmable digital portion of the component that controls components in the dedicated digital or analog portions using state transition information. The programmable controller is configured to accommodate a broad spectrum of state transition information and is capable of emulating a plurality of hardwired finite state machines
1. A transceiver comprising:
a plurality of independently controlled components, each independently controlled component including a programmable digital portion;
a unit controller in the programmable digital portion of each independently controlled component, each unit controller associated with each of the plurality of independently controlled components including a programmable processor component configured to receive and to execute state transition information;
an interface component including a baseband interface configured to couple to a baseband processor; and
a bus and distribution system comprising a plurality of dedicated bus systems to allow the independently controlled components to operate more efficiently than over a single bus, the plurality of dedicated bus systems including:
a time accurate strobe distribution system configured to provide command instructions to each of the unit controllers and a central processing sub-system; and
a global time distribution system, distinct from the time accurate strobe distribution system, configured to provide a timing signal to the central processing sub-system and each unit controller, the timing signal synchronizes the central processing sub-system and each unit controller.
2. The transceiver of claim 1 , wherein the bus and distribution system further comprises: a signaling bus system configured to provide and to receive event notifications from each unit controller and the central processing sub-system, the event notifications indicating when the unit controller or central processing sub-system should perform a task.
3. The transceiver of claim 1 , wherein the bus and distribution system is configured to provide configuration information from the central processing sub-system to a plurality of unit controllers of the plurality of independently controlled components; and
wherein the transceiver includes a logic interface component configured to provide configuration information to the plurality of unit controllers over the bus and distribution system.
4. The transceiver of claim 3 , wherein the central processing sub-system is configured to receive configuration macros, to decode the configuration macros, and to provide configuration information to each unit controller based on the configuration macros.
5. The transceiver of claim 1 , further comprising: a multi-core debug system connected to a debug bus system configured to provide debug instructions to each unit controller and the central processing sub-system and to receive debug results from each unit controller and the central processing sub-system.
6. The transceiver of claim 1 , wherein each unit controller is configured to control a analog portion and a digital portion within a respective independently controlled component.
7. The transceiver of claim 1 , wherein each independently controlled component is independently controlled by its respective unit controller.
8. The transceiver of claim 1 , wherein the interface component of the transceiver includes the central processing sub-system.
9. The transceiver of claim 1 , wherein a first independently controlled component of the plurality of independently controlled components includes the interface component.
10. The transceiver of claim 1 , wherein one or more unit controllers of the plurality of independently controlled components includes a pipeline processor.
11. The transceiver of claim 10 , wherein the pipeline processor is a multi-stage pipeline processor configured to emulate a plurality of finite state machines.
12. The transceiver of claim 10 , wherein the pipeline processor includes multiple parallel data paths that are reconfigurable with each clock cycle of the pipeline processor.
13. The transceiver of claim 10 . wherein the pipeline processor is configured to receive a plurality of threads, each thread including state transition information, and to process, in a fixed order, the plurality of threads.