IP Library Granted Patent US 8,397,016
Granted Patent B2
US 8,397,016 · App. 12/650,966 · Granted Mar 12, 2013

Efficient use of hybrid media in cache architectures

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,397,016
App. No.
12/650,966
Granted
Mar 12, 2013
Kind
B2
Abstract

A multi-tiered cache manager and methods for managing multi-tiered cache are described. Multi-tiered cache manager causes cached data to be initially stored in the RAM elements and selects portions of the cached data stored in the RAM elements to be moved to the flash elements. Each flash element is organized as a plurality of write blocks having a block size and wherein a predefined maximum number of writes is permitted to each write block. The portions of the cached data may be selected based on a maximum write rate calculated from the maximum number of writes allowed for the flash device and a specified lifetime of the cache system.

Claims (18)

1. A multi-tiered cache system, comprising:

a plurality of cache elements including RAM and flash elements; and

a manager configured to control access to the cache elements,

wherein the manager causes cached data to be initially stored in the RAM elements and selects portions of the cached data stored in the RAM elements to be written to the flash elements based on at least a maximum write rate calculated from the maximum number of writes associated with the flash elements and a specified lifetime of the cache system,

wherein each RAM element is organized as a plurality of RAM blocks, and

wherein each of the portions of the cached data is moved when no RAM block is available for storing new data, and

wherein no RAM block is available when no available RAM block is large enough to store new cached data.

2. The system of claim 1 , wherein each flash element is organized as a plurality of write blocks having a block size and wherein a predefined maximum number of writes is permitted for each write block.

3. The system of claim 1 , wherein each of the portions of the cached data is moved to a designated write block and the portions of the cached data are substantially equal in size to the size of the designated write block.

4. The system of claim 1 , wherein each RAM element is organized as a plurality of RAM blocks and wherein each of the portions of the cached data is moved when no RAM block is available for storing new data.

5. The system of claim 4 , wherein RAM blocks are unavailable that contain cached data.

6. A method for managing mixed-media cache system, comprising:

receiving data for caching;

assigning the received data into one or more blocks;

optionally writing aged data stored in a RAM block to flash memory; and

storing the one or more blocks in RAM, wherein moving the aged data stored in the RAM block includes selecting the RAM block based on factors including the size of the one or more blocks and the age of the moved data, with a maximum write rate calculated from a maximum number of writes associated with flash memory elements and a specified lifetime of the cache system,

wherein each of the portions of the cached data is moved when no RAM block is available for storing new data, and

wherein no RAM block is available when no available RAM block is large enough to store new cached data.

Assignments (14)
CORRECTIVE ASSIGNMENT TO REMOVE US PATENT NO. 9013874 PREVIOUSLY RECORDED UNDER REEL AND FRAME 064272/0249. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 17, 2024
From: VSIP HOLDINGS LLC (F/K/A VIOLIN SYSTEMS LLC)
To: INNOVATIONS IN MEMORY LLC
Reel/Frame 068998/0780 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 13, 2023
From: VSIP HOLDINGS LLC (F/K/A VIOLIN SYSTEMS LLC)
To: INNOVATIONS IN MEMORY LLC
Reel/Frame 064272/0249 →
RELEASE OF SECURITY INTEREST Recorded Jun 16, 2021
From: SILICON VALLEY BANK
To: VSIP HOLDINGS LLC (F/K/A VIOLIN SYSTEMS LLC (F/K/A VIOLIN MEMORY, INC.))
Reel/Frame 056600/0186 →
CHANGE OF NAME Recorded May 25, 2021
From: VIOLIN SYSTEMS LLC
To: VSIP HOLDINGS LLC
Reel/Frame 056366/0849 →
RELEASE OF SECURITY INTEREST Recorded Jan 22, 2018
From: SILICON VALLEY BANK
To: VIOLIN SYSTEMS LLC
Reel/Frame 044686/0688 →
CHANGE OF NAME Recorded Dec 19, 2017
From: VIOLIN MEMORY, INC.
To: VIOLIN SYSTEMS LLC
Reel/Frame 044908/0680 →
SECURITY INTEREST Recorded Aug 27, 2014
From: VIOLIN MEMORY, INC.
To: SILICON VALLEY BANK
Reel/Frame 033645/0834 →
RELEASE OF SECURITY INTEREST Recorded Aug 26, 2014
From: COMERICA BANK
To: VIOLIN MEMORY, INC.
Reel/Frame 033617/0360 →
RELEASE OF SECURITY INTEREST Recorded Aug 22, 2014
From: TRIPLEPOINT CAPITAL LLC
To: VIOLIN MEMORY, INC.
Reel/Frame 033591/0759 →
SECURITY AGREEMENT Recorded Jul 19, 2013
From: VIOLIN MEMORY, INC.
To: COMERICA BANK, A TEXAS BANKING ASSOCIATION
Reel/Frame 030833/0440 →
SECURITY AGREEMENT Recorded May 16, 2013
From: VIOLIN MEMORY, INC.
To: TRIPLEPOINT CAPITAL LLC
Reel/Frame 030426/0821 →
CHANGE OF NAME Recorded Aug 10, 2010
From: GEAR SIX, INC.
To: GEAR6(ASSIGNMENT FOR THE BENEFIT OF CREDITORS)LLC
Reel/Frame 024813/0027 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 10, 2010
From: GEAR6(ASSIGNMENT FOR THE BENEFIT OF CREDITORS)LLC
To: VIOLIN MEMORY, INC.
Reel/Frame 024814/0008 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 7, 2010
From: TALAGALA, NISHA; KERCHEVAL, BERRY; PATTERSON, MARTIN; PERNICKA, EDWARD; BOWEN, JAMES
To: GEAR SIX, INC.
Reel/Frame 024647/0658 →