Thin film transistor array panel and method for manufacturing the same
View Patent ↗A thin film transistor array panel includes an insulating substrate. A gate line is formed on the insulating substrate and has a gate electrode. A gate insulating layer is formed on the gate line. A semiconductor layer is formed on the gate insulating layer and overlaps the gate electrode. Diffusion barriers are formed on the semiconductor layer and contain nitrogen. A data line crosses the gate line and has a source electrode partially contacting the diffusion barriers and a drain electrode partially contacting the diffusion barriers and facing the source electrode. The drain electrode is on the gate electrode. A pixel electrode is electrically connected to the drain electrode.
1. A thin film transistor array panel comprising:
an insulating substrate;
a gate line formed on the insulating substrate and comprising a gate electrode;
a gate insulating layer formed on the gate line;
a semiconductor layer formed on the gate insulating layer and overlapping the gate electrode;
a first ohmic contact layer formed on the semiconductor layer;
a diffusion barrier layer comprising nitrogen formed on the first ohmic contact layer;
a second ohmic contact layer formed on the diffusion barrier layer;
a data line crossing the gate line and comprising a source electrode and a drain electrode on the diffusion barrier layer;
a passivation layer on the data line; and
a pixel electrode formed on the passivation layer and electrically connected to the drain electrode.
2. The thin film transistor array panel of claim 1 , wherein the semiconductor layer has substantially the same planar pattern as the data line except for a portion of the semiconductor layer that is between the source and drain electrodes.
3. The thin film transistor array panel of claim 1 , wherein the gate line comprise copper or a copper alloy.
4. The thin film transistor array panel of claim 1 , further comprising red, green, and blue color filters under the pixel electrode on the insulating substrate.
5. The thin film transistor array panel of claim 1 , wherein the data line comprise a Cu—Mn (copper-manganese) alloy.
6. The thin film transistor array panel of claim 5 , wherein a surface of the data line comprises a Mn oxide.
7. A method for manufacturing a thin film transistor array panel, comprising:
forming a gate line comprising a gate electrode on an insulating substrate;
forming a gate insulating layer and an a-Si layer;
forming a first ohmic contact layer doped with a conductive impurity, a diffusion barrier layer and a second ohmic contact layer;
forming a data line comprising source and drain electrodes overlapping the second ohmic contact layer;
forming a passivation layer on the data line; and
forming a pixel electrode electrically connected to the drain electrode.
8. The method of claim 7 , wherein the gate line comprises copper or a copper alloy.
9. The method of claim 7 , wherein the data line comprises a Cu—Mn alloy.
10. The method of claim 7 , wherein the diffusion barrier layer comprises nitrogen and a same material as the first ohmic contact layer.
11. The method of claim 7 , wherein the diffusion barrier layer is formed through a plasma treatment.
12. The method of claim 7 , wherein the a-Si layer, the first ohmic contact layer, the diffusion barrier layer, the second ohmic contact layer and the data line having the source and drain electrode are formed through a single photo exposure process.
13. The method of claim 7 , wherein the diffusion barrier layer comprises nitrogen and a same material as the first ohmic contact layer.
14. A thin film transistor array panel comprising:
a gate line comprising a gate electrode on an insulating substrate;
a gate insulating layer;
a semiconductor layer;
a first ohmic contact layer doped with a conductive impurity, a diffusion barrier layer and a second ohmic contact layer;
a data line comprising a source electrode and a drain electrode overlapping the second ohmic contact layer;
a passivation layer on the data line; and
a pixel electrode electrically connected to the drain electrode.
15. The transistor array panel of claim 14 , wherein the semiconductor layer has substantially the same planar pattern as the data line except for a portion of the semiconductor layer that is between the source and drain electrodes.
16. The transistor array panel of claim 14 , wherein the gate line comprise copper or a copper alloy.
17. The transistor array panel of claim 14 , further comprising red, green, and blue color filters under the pixel electrode on the insulating substrate.
18. The transistor array panel of claim 14 , wherein the data line comprise a Cu—Mn (copper-manganese) alloy.
19. The transistor array panel of claim 18 , wherein a surface of the data line comprises a Mn oxide.
20. The transistor array panel of claim 14 , wherein the diffusion barrier layer comprises nitrogen and a same material as the first ohmic contact layer.