Method and system for addressing a plurality of ethernet controllers integrated into a single chip which utilizes a single bus interface
View Patent ↗A method for processing network data is disclosed and may include receiving data via a single bus interface to which each of a plurality of Ethernet controllers are coupled, where the Ethernet controllers are integrated within a single chip. A particular one of the integrated Ethernet controllers may be identified based on information within the received data. The particular one of the integrated Ethernet controllers may be granted access to a shared resource within the single chip. The access to the shared resource may be granted using at least one semaphore register within the shared resource. The particular one of the integrated Ethernet controllers may be granted access to the single bus interface. The information may include a bus identifier, a bus device identifier and/or a bus function identifier. The shared resource may include a nonvolatile memory (NVM).
1. A method for processing network data, the method comprising:
receiving data via a single bus interface to which each of a plurality of Ethernet controllers are coupled, said plurality of Ethernet controllers integrated within a single chip;
identifying a particular one of said plurality of integrated Ethernet controllers based on information within said received data; and
granting said particular one of said integrated Ethernet controllers, access to a shared resource within said single chip, wherein said bus interface is independent of said shared resource.
2. The method according to claim 1 , comprising granting said access to said shared resource using at least one semaphore register within said shared resource.
3. The method according to claim 1 , comprising granting said particular one of said integrated Ethernet controllers access to said single bus interface.
4. The method according to claim 1 , wherein said information comprises a bus identifier, a bus device identifier and a bus function identifier.
5. The method according to claim 1 , wherein said shared resource comprises a nonvolatile memory (NVM).
6. The method according to claim 5 , wherein said NVM may comprise one or more of a flash memory interface, an EEPROM interface, a Serial Programming Interface (SPI), and/or a System Management Bus (SMBus).
7. The method according to claim 5 , wherein said NVM stores device configuration information for at least one of said plurality of Ethernet controllers.
8. The method according to claim 1 , wherein said shared resource comprises a general purpose input/output (GPIO) interface.
9. The method according to claim 8 , comprising utilizing a contention resolution contention scheme to prevent dual access to said GPIO interface by said plurality of Ethernet controllers.
10. The method according to claim 1 , wherein said single bus interface is one of a PCI bus interface, a PCI-X bus interface, and a variant of said PCI bus interface.
11. The method according to claim 1 , wherein one or more of said plurality of Ethernet controllers are Fibre channel controllers.
12. The method according to claim 1 , wherein said access is granted to a host process running on a host.
13. A system for processing network data, the system comprising:
a single bus interface;
a plurality of Ethernet controllers, each of said plurality of Ethernet controllers integrated within a single chip and coupled to said single bus interface; and
an arbitrator within said single chip, wherein said arbitrator enables:
receiving of data via said single bus;
identifying a particular one of said plurality of integrated Ethernet controllers based on information within said received data; and
granting said particular one of said integrated Ethernet controllers, access to a shared resource within said single chip, wherein said bus interface is independent of said shared resource.
14. The system according to claim 13 , wherein said arbitrator enables granting said access to said shared resource using at least one semaphore register within said shared resource.
15. The system according to claim 13 , wherein said arbitrator enables granting said particular one of said integrated plurality of Ethernet controllers access to said single bus interface.
16. The system according to claim 13 , wherein said information comprises a bus identifier, a bus device identifier and a bus function identifier.
17. The system according to claim 13 , wherein said shared resource comprises a nonvolatile memory (NVM).
18. The system according to claim 17 , wherein said NVM may comprise one or more of a flash memory interface, an EEPROM interface, a Serial Programming Interface (SPI), and/or a System Management Bus (SMBus).
19. The system according to claim 17 , wherein said NVM stores device configuration information for at least one of said plurality of Ethernet controllers.
20. The system according to claim 13 , wherein said shared resource comprises a general purpose input/output (GPIO) interface.
21. The system according to claim 20 , wherein said arbitrator enables utilizing a contention resolution contention scheme to prevent dual access to said GPIO interface by said plurality of Ethernet controllers.
22. The system according to claim 13 , wherein said single bus interface is one of a PCI bus interface, a PCI-X bus interface, and a variant of said PCI bus interface.
23. The system according to claim 13 , wherein one or more of said plurality of Ethernet controllers are Fibre channel controllers.
24. The system according to claim 13 , wherein said arbitrator grants said access to a host process running on a host.