IP Library Granted Patent US 8,001,286
Granted Patent B2
US 8,001,286 · App. 12/654,345 · Granted Aug 16, 2011

Multipurpose and programmable pad for an integrated circuit

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Quick Facts
Patent No.
US 8,001,286
App. No.
12/654,345
Granted
Aug 16, 2011
Kind
B2
Abstract

A multi-port SERDES transceiver includes multiple parallel and serial ports, and the flexibility to connect any one of the parallel or serial ports to another parallel or serial port. The ports include programmable pads that are capable of supporting multiple different data protocols, timing protocols, electrical specifications, and input-output functions. A management data IO pad also enables the transceiver to support different electrical requirements and data protocols at the same time. The substrate layout of the transceiver is configured so that the parallel ports and the serial ports are on the outer perimeter. A logic core is at the center, where the logic core operates the serial and parallel data ports, and the bus that connects the data ports. The bus can be described as a “ring” structure (or donut “structure”) around the logic core, and is configured between the logic core and the data ports.

Claims (37)

1. A transceiver, comprising:

a first port having a first programmable pad, the first programmable pad being configurable to operate according to a first specified electrical specification from among a plurality of electrical specifications and a first specified data protocol from among a plurality of data protocols; and

a second port having a second programmable pad, the second programmable pad being configurable to operate according to a second specified electrical specification from among the plurality of electrical specifications and a second specified data protocol from among the plurality of data protocols,

wherein the first port and the second port are arranged on a substrate in a rotational symmetric layout, the rotational symmetric layout of the substrate allowing the transceiver to maintain its functionality and configuration when rotated.

2. The transceiver of claim 1 , wherein the first port is a serial port and the second port is a parallel port, the first programmable pad and the second programmable pad forming part of the serial port and the parallel port, respectively.

3. The transceiver of claim 1 , further comprising:

a bus configured and arranged to communicatively couple the first port and the second port.

4. The transceiver of claim 3 , wherein the bus is arranged to form a ring structure around a central logic core.

5. The transceiver of claim 1 , further comprising:

a pad control system constructed and arranged to configure the first programmable pad to operate in accordance with the first specified data protocol and the first specified electrical specification and the second programmable pad to operate in accordance with the second specified data protocol and the second specified electrical specification.

6. The transceiver of claim 5 , wherein the pad control system comprises:

an input controller to configure at least one of a group consisting of: the first programmable pad and the second programmable pad to receive at least one of a group consisting of: a data signal and a control signal.

7. The transceiver of claim 5 , wherein the pad control system comprises:

an output controller to configure at least one of a group consisting of: the first programmable pad and the second programmable pad to send at least one of a group consisting of: a data signal and a control signal.

8. The transceiver of claim 1 , wherein the first port is configured to perform a parallel to serial conversion when the first port receives parallel data.

9. The transceiver of claim 1 , wherein the first port is configured to perform a serial to parallel conversion when the first port receives serial data.

10. The transceiver of claim 1 , wherein at least one of a group consisting of: an operating voltage of the first programmable pad and an operating voltage of the second programmable pad is defined according to the specified electrical specification.

11. The transceiver of claim 1 , wherein the first port and the second port are configured to either send or receive data after having been configured to comply with the specified data protocol and the specified electrical specification.

12. The transceiver of claim 1 , wherein the rotational symmetric layout of the substrate allows the transceiver to be connected to another communications device in a first position or a second position, the first position being rotated from the second position, and wherein the transceiver is configured to connect to the another communication in both the first position and the second position without having to reconfigure either device.

13. A transceiver including a serial port and a parallel port, comprising:

a first programmable pad configured and arranged to foam part of the serial port; and

a second programmable pad configured and arranged to form part of the parallel port, the first serial port and the parallel port being arranged on a substrate in a rotational symmetric layout, the rotational symmetric layout of the substrate allowing the transceiver to maintain its functionality and configuration when rotated,

wherein said first programmable pad and said second programmable pad are configurable to operate according to a plurality of electrical specifications and a plurality of data protocols.

14. The transceiver of claim 13 , further comprising:

a bus configured and arranged to communicatively couple the serial port and the parallel port.

15. The transceiver of claim 14 , wherein the bus is arranged to form a ring structure around a central logic core.

16. The transceiver of claim 13 , further comprising:

a pad control system constructed and arranged to configure the first programmable pad to operate in accordance with the first specified data protocol and the first specified electrical specification and the second programmable pad to operate in accordance with the second specified data protocol and the second specified electrical specification.

17. The transceiver of claim 16 , wherein the pad control system comprises:

an input controller to configure at least one of a group consisting of: the first programmable pad and the second programmable pad to receive at least one of a group consisting of: a data signal and a control signal.

18. The transceiver of claim 16 , wherein the pad control system comprises:

an output controller to configure at least one of a group consisting of: the first programmable pad and the second programmable pad to send at least one of a group consisting of: a data signal and a control signal.

19. The transceiver of claim 13 , wherein the serial port is configured to perform a parallel to serial conversion when the serial port receives parallel data.

20. The transceiver of claim 13 , wherein the parallel port is configured to perforin a serial to parallel conversion when the parallel port receives serial data.

21. The transceiver of claim 13 , wherein at least one of a group consisting of: an operating voltage of the first programmable pad and an operating voltage of the second programmable pad is defined according to the specified electrical specification.

22. The transceiver of claim 13 , wherein the serial port and the parallel port are configured to either send or receive data after having been configured to comply with the specified data protocol and the specified electrical specification.

23. The transceiver of claim 13 , wherein the rotational symmetric layout of the substrate allows the transceiver to be connected to another communications device in a first position or a second position, the first position being rotated from the second position, and wherein the transceiver is configured to connect to the another communication in both the first position and the second position without having to reconfigure either device.

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT THE PROPERTY NUMBERS PREVIOUSLY RECORDED AT REEL: 47630 FRAME: 344. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Mar 21, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048883/0267 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER TO 9/5/2018 PREVIOUSLY RECORDED AT REEL: 047196 FRAME: 0687. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047630/0344 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047196/0687 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2009
From: TRAN, HOANG T.; BAUMER, HOWARD A.
To: BROADCOM CORPORATION
Reel/Frame 023728/0088 →