IP Library Granted Patent US 8,097,486
Granted Patent B2
US 8,097,486 · App. 12/656,925 · Granted Jan 17, 2012

Method for producing a solid-state imaging element

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Quick Facts
Patent No.
US 8,097,486
App. No.
12/656,925
Granted
Jan 17, 2012
Kind
B2
Abstract

There is provided a solid-state imaging element having a light receiving part generating charges by light irradiation, and a source/drain region of a transistor, both formed in a semiconductor layer. The solid-state imaging element includes a non-silicided region including the light receiving part, in which surfaces of the source/drain region and a gate electrode of the transistor are not silicided; and a silicided region in which the surfaces of the source/drain region and the gate electrode of the transistor are silicided. The non-silicided region has a sidewall formed on a side surface of the gate electrode of the transistor, a hydrogen supply film formed to cover the semiconductor layer, the gate electrode, and the sidewall, and a salicide block film formed on the hydrogen supply film to prevent silicidation. The silicided region has a sidewall formed on the side surface of the gate electrode of the transistor.

Claims (14)

1. A method for producing a solid-state imaging element having a silicided region including a transistor in which surfaces of a source/drain region and a gate electrode of the transistor are at least silicided; and a non-silicided region including a transistor in which surfaces of the source/drain region and the gate electrode of the transistor are not silicided, the method comprising the steps of:

forming a gate electrode on a semiconductor layer in each region;

forming an insulating film to cover the semiconductor layer and each gate electrode, the step of forming the insulating film to cover each gate electrode comprises the step of forming a silicon oxide film to cover each gate electrode and forming a silicon nitride film on the silicon oxide film;

etching the insulating film to form a sidewall on a side surface of the gate electrode;

forming each source/drain region in the semiconductor layer using each gate electrode and each sidewall as masks;

forming a hydrogen supply film to cover the gate electrodes, the sidewalls, the source/drain regions, and a light receiving region formed in the semiconductor layer to generate charges by light irradiation;

forming a salicide block film on the hydrogen supply film;

removing the hydrogen supply film and the salicide block film except for the non-silicided region; and

forming a metal silicide film by forming a metal film on a substrate and then thermally treating the metal film to silicide an upper part of the gate electrode and an upper part of the source/drain region in the silicided region based on reaction of the metal film with silicon.

2. A method for producing a solid-state imaging element according to claim 1 , further comprising the step of forming a silicon oxide film to cover each gate electrode and forming a silicon nitride film on the silicon oxide film in the step of forming the insulating film to cover each gate electrode.

3. A method for producing a solid-state imaging element according to claim 1 , further comprising the step of etching the insulating film in the silicided region and the non-silicided region to form each sidewall having an identical structure in each of the silicided region and the non-silicided region.

4. A method for producing a solid-state imaging element according to claim 1 , further comprising the step of performing source/drain injection into the silicided region and the non-silicided region under identical conditions in the step of forming each source/drain region.

5. A method for producing a solid-state imaging element according to claim 1 , further comprising the step of forming the hydrogen supply film by a silicon nitride film deposited by plasma CVD using an ultraviolet light source.

6. A method for producing a solid-state imaging element according to claim 1 , further comprising the step of forming the salicide block film by an SiN film formed by low pressure CVD.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 19, 2016
From: SONY CORPORATION
To: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Reel/Frame 040419/0001 →