Processor instruction used to perform a matrix test to generate a memory-related trap

1. A method comprising:

fetching an instruction that comprises:

a first set of one or more bits identifying the instruction; and

a second set of one or more bits associated with a first address value;

executing the instruction to determine whether to perform a trap, wherein executing the instruction includes selecting from a plurality of tests at least one test for determining whether to perform a trap and carrying out the at least one test; wherein:

the second set of one or more bits is used in the determination of whether to perform the trap; and

the plurality of tests includes a matrix test that determines whether a data value being stored as pointed to by the first address value is escaping from one of a plurality of managed memory types to another one of the plurality of managed memory types and generates a trap in the event that the data value is determined to be escaping from one of the plurality of managed memory types to another one of the plurality of managed memory types, wherein the matrix test is based on a matrix associated with garbage collection and a matrix entry whose location within the matrix is determined using bits that are included in the instruction as indices into the matrix.

2. A method as recited in claim 1 , wherein the instruction is associated with garbage collection.

3. A method as recited in claim 1 , wherein the second set of one or more bits includes one or more of the following: an operand of the instruction, the first address value, a value related to a memory location containing the first address value, an identifier associated with a register containing the first address value, and an identifier associated with a register containing a value related to a memory location containing the first address value.

4. A method as recited in claim 1 , wherein one or more bits of the instruction specify a configuration associated with the instruction; and the configuration includes one or more of the following: an instruction format specification, an instruction field format specification, configuration associated with an operation of the instruction, and specification of the at least one test used in making the determination of whether to perform the trap.

5. A method as recited in claim 1 , wherein the at least one test used in making the determination of whether to perform the trap is specified at least in part by one or more of the following: the first set of one or more bits identifying the instruction, an indication of a user level processing, system configuration data, processor configuration data, program configuration data, dynamically updated data, and configuration data associated with the instruction.

6. A method as recited in claim 1 , wherein before determining whether to perform the trap, the first address value is read from a memory location associated with a second address value associated with a third group of one or more bits included in the instruction.

7. A method as recited in claim 1 , wherein in the event it is determined to not perform the trap, the first address value is stored to a memory location associated with a second address value associated with a third group of one or more bits included in the instruction.

8. A method as recited in claim 1 , wherein the first address value includes one or more bits specifying one or more of the following: a marker portion, an address type portion, a frame ID portion, and a location reference portion.

9. A method as recited in claim 1 , wherein performing the trap includes performing one or more of the following: redirecting execution of a program, executing a trap handler, modifying a program counter (PC) value, and logging the trap.

10. A method as recited in claim 1 , wherein the matrix entry is located by using one or more bits of a second address value associated with a third group of one or more bits included in the instruction.

11. A method as recited in claim 10 , wherein a memory location is associated with the second address value.

12. A method as recited in claim 1 , wherein the plurality of tests further includes: a translation look-aside buffer (TLB) test that is based at least in part on a TLB entry associated with the first address value, a frame test that determines whether the first address value is associated with stack allocated memory, and a null check that determines whether the first address value includes a null value.

13. A method as recited in claim 12 , wherein when determining whether to perform the trap, a translation look-aside buffer (TLB) entry is used to determine whether the TLB entry is protected.

14. A method as recited in claim 13 , wherein a protected TLB entry is associated with a memory location undergoing garbage collection.

15. A method as recited in claim 1 , wherein the plurality of tests further includes a frame test that uses the second set of one or more bits to determine whether to perform the trap, and the frame test is based at least in part on determining whether the first address value is associated with stack allocated memory in which one or more objects are allocated.

16. A method as recited in claim 15 , wherein the frame test is based at least in part on a stack frame identifier included in the first address value.

17. A method as recited in claim 15 , wherein the instruction further comprises a third set of one or more bits associated with a second address value used in the determination; and the frame test is based at least in part on determining whether the second address value is associated with stack allocated memory.

18. A method as recited in claim 17 , wherein the frame test is based at least in part on comparing a first stack frame identifier included in the first address value with a second frame identifier included in the second address value.

19. A method as recited in claim 18 , wherein the comparison includes determining whether one frame identifier is of a deeper stack frame than the stack frame of another frame identifier.

20. A system comprising:

a processor configured to:

fetch an instruction that comprises:

a first set of one or more bits identifying the instruction; and

a second set of one or more bits associated with a first address value; and

execute the instruction to determine whether to perform a trap, wherein executing the instruction includes selecting from a plurality of tests at least one test for determining whether to perform a trap and carrying out the at least one test; wherein:

the second set of one or more bits is used in the determination of whether to perform the trap; and

the plurality of tests includes a matrix test that determines whether a data value being stored as pointed to by the first address value is escaping from one of a plurality of managed memory types to another one of the plurality of managed memory types and generates a trap in the event that the data value is determined to be escaping from one of the plurality of managed memory types to another one of the plurality of managed memory types, wherein the matrix test is based on a matrix associated with garbage collection and a matrix entry whose location within the matrix is determined using bits that are included in the instruction as indices into the matrix; and

a memory coupled with the processor, wherein the memory is configured to provide the processor with the instruction.

21. A system as recited in claim 20 , wherein the second set of bits includes one or more of the following: an operand of the instruction, the first address value, a value related to a memory location containing the first address value, an identifier associated with a register containing the first address value, and an identifier associated with a register containing a value related to a memory location containing the first address value.

22. A system as recited in claim 20 , wherein the at least one test used in making the determination of whether to perform the trap is specified at least in part by one or more of the following: the first set of bits identifying the instruction, an indication of a user level processing, system configuration data, processor configuration data, program configuration data, dynamically updated data, and configuration data associated with the instruction.

23. A system as recited in claim 20 , wherein the plurality of tests further includes a frame test based at least in part on determining whether the first address value is associated with stack allocated memory in which one or more objects are allocated.

24. A system as recited in claim 23 , wherein the frame test is based at least in part on a stack frame identifier included in the first address value.

25. A system as recited in claim 23 , wherein the instruction further comprises a third set of one or more bits associated with a second address value used in the determination; and the frame test is based at least in part on determining whether the second address value is associated with stack allocated memory.

26. A system as recited in claim 23 , wherein the plurality of tests further includes: a translation look-aside buffer (TLB) test that is based at least in part on a TLB entry associated with the first address value, a frame test that determines whether the first address value is associated with stack allocated memory, and a null check that determines whether the first address value includes a null value.