Semiconductor device and method of manufacturing the same
View Patent ↗In a method of manufacturing a high withstanding voltage MOSFET, a region to be doped with impurities and a region to be doped with no impurity are provided when ion implantation of the impurities is performed in the channel forming region, for controlling a threshold voltage. The region to be doped with no impurity is suitably patterned so that impurity concentration of the channel forming region near boundaries between a well region and a source region and between the well region and a drain region having the same conductivity type as the well region may be increased, to thereby induce a reverse short channel effect. By canceling a short channel effect with the reverse short channel effect induced by the above-mentioned method, the short channel effect of the high withstanding voltage MOSFET may be suppressed.
1. A method of manufacturing a semiconductor device, comprising:
forming a well region of a first conductivity type on a semiconductor substrate;
forming a low concentration source region of a second conductivity type and a low concentration drain region of the second conductivity type in the well region, the low concentration source region and the low concentration drain region being spaced apart from each other;
forming a high concentration source region of the second conductivity type in the low concentration source region;
forming a high concentration drain region of the second conductivity type in the low concentration drain region;
forming a first field oxide film in the low concentration source region;
forming a second field oxide film in the low concentration drain region; and
providing a region to be doped with impurities for threshold voltage adjustment and a region to be doped with no impurity in a channel forming region located between the low concentration source region and the low concentration drain region, and performing channel doping therein.
2. A method of manufacturing a semiconductor device according to claim 1 , wherein:
the region to be doped with the impurities for threshold voltage adjustment and the region to be doped with no impurity are formed in a grid-like pattern including a rectangular window; and
the region to be doped with no impurity corresponds to a portion corresponding to the rectangular window of the grid when the region to be doped with the impurities corresponds to a portion corresponding to a frame of the grid, and the region to be doped with the impurities corresponds to the portion corresponding to the rectangular window of the grid when the region to be doped with no impurity corresponds to the portion corresponding to the frame of the grid.
3. A method of manufacturing a semiconductor device according to claim 2 , wherein, when the impurities for threshold voltage adjustment are of the first conductivity type, the portion corresponding to the frame of the grid is doped with the impurities.
4. A method of manufacturing a semiconductor device according to claim 2 , wherein, when the impurities for threshold voltage adjustment are of the second conductivity type, the portion corresponding to the rectangular window of the grid is doped with the impurities.
5. A semiconductor device, comprising:
a well region of a first conductivity type formed along a main surface of a semiconductor substrate;
a low concentration source region of a second conductivity type and a low concentration drain region of the second conductivity type, which are formed in the well region and spaced apart from each other;
a high concentration source region of the second conductivity type formed in the low concentration source region;
a high concentration drain region of the second conductivity type formed in the low concentration drain region;
a first field oxide film formed in the low concentration source region, the first field oxide film having one end portion in contact with the high concentration source region;
a second field oxide film formed in the low concentration drain region, the second field oxide film having one end portion in contact with the high concentration drain region;
a channel forming region located between the low concentration source region and the low concentration drain region; and
a gate electrode formed above the channel forming region through a gate oxide film,
wherein the channel forming region comprises a region doped with first conductivity type impurities at a first impurity concentration at a peripheral portion near boundaries between the low concentration source region and the channel forming region and between the low concentration drain region and the channel forming region, and a region doped with the first conductivity type impurities at a second impurity concentration at a non-peripheral portion.
6. A semiconductor device according to claim 5 , wherein the first impurity concentration of the first conductivity type impurities for threshold voltage adjustment is higher than the second impurity concentration.