Physical layer device having an analog SERDES pass through mode
View Patent ↗A physical layer device (PLD) includes a first serializer-deserializer (SERDES) device and a second SERDES device. Each SERDES device includes an analog portion with a serial port that is configured to communicate serial data with various network devices, and a digital portion that is configured to communicate parallel data with other various network devices. The PLD includes a first signal path that is configured to route serial data signals between the analog portions of the SERDES devices, bypassing the digital portions of the SERDES devices. Therefore, the SERDES devices can directly communicate serial data without performing parallel data conversion. A second signal path is configured to route recovered clock and data signals between the analog portions of the SERDES devices, but still bypassing the digital portions of the SERDES devices. The recovered clock and data signals are then regenerated before being transmitted over a network device.
1. A data communications device, comprising:
a first serializer-deserializer (SERDES) device including a first analog portion and a first digital portion, said first analog portion having a first serial port and a clock and data recovery module coupled to a receive portion of said first serial port, and said first digital portion coupled to a serial data output of said clock and data recovery module;
a second SERDES device including a second analog portion and a second digital portion, said second analog portion having a second serial port and a data serializer and clock generator module coupled to a transmit portion of said second serial port, and said second digital portion coupled to a serial data input of said data serializer and clock generator module; and
a first signal path that connects said serial data output of said clock and data recovery module to said serial data input of said data serializer and clock generator module, bypassing said first and second digital portions.
2. The data communications device of claim 1 , wherein said first signal path carries serial data signals between said first serial port of said first SERDES device and said second serial port of said second SERDES device through said clock and data recovery module and said data serializer and clock generator module.
3. The data communications device of claim 1 , wherein said first signal path is coupled between a first node in said first SERDES device and a second node in said second SERDES device, said first node defined between said serial data output of said clock and data recovery module and said first digital portion of said first SERDES device, said second node defined between said serial data input of said data serializer and clock generator module and said second digital portion of said second SERDES device.
4. The data communications device of claim 3 , further comprising a second signal path that connects said first serial port to said second serial port, bypassing said clock and data recovery module and said data serializer and clock generator module.
5. The data communications device of claim 4 , wherein said second signal path is coupled between a third node of said first SERDES device and a fourth node of said second SERDES device, said third node defined between said receive portion of said first serial port and an input of said clock and data recovery module, said fourth node defined between said transmit portion of said second serial port and an output of said data serializer and clock generator module.
6. The data communications device of claim 1 , wherein said data communications device is part of a network device.
7. The data communications device of claim 1 , wherein said data communications device is part of a data switch operating in a network environment.
8. The data communications device of claim 1 , wherein said first serial port interfaces with a network device.
9. The data communications device of claim 8 , wherein said network device includes a media access controller.
10. The data communications device of claim 1 , wherein said second serial port interfaces with a fiber module.
11. The data communications device of claim 1 , wherein said first serial port of said first SERDES device interfaces with a network device.
12. The data communications device of claim 11 , wherein said network device is an Ethernet device.
13. The data communications device of claim 1 , wherein:
said first serial port interfaces with a media access controller;
said second serial port interfaces with a fiber module.
14. The data communications device of claim 1 , wherein said first SERDES device, said second SERDES device, and said first signal path are disposed on a common substrate.
15. The data communications device of claim 14 , wherein said common substrate is a CMOS substrate.
16. The data communications device of claim 14 , further comprising a second signal path that connects said first serial port to said second serial port, bypassing said clock and data recovery module and said data serializer and clock generator module, wherein said second signal path is disposed on said common substrate with said first SERDES device, said second SERDES device, and said first signal path.
17. The data communications device of claim 1 , wherein said data communications device forms part of a local communications node, and wherein said first and second SERDES devices are located on a common integrated circuit substrate at said local communications node.
18. A data communications device, comprising:
a first serializer-deserializer (SERDES) device including a first analog portion and a first digital portion, said first analog portion having a first serial port and a clock and data recovery module coupled to a receive portion of said first serial port, and said first digital portion coupled to a serial data output of said clock and data recovery module;
a second SERDES device including a second analog portion and a second digital portion, said second analog portion having a second serial port and a data serializer and clock generator module coupled to a transmit portion of said second serial port, and said second digital portion coupled to a serial data input of said data serializer and clock generator module; and
means for routing said serial data output of said clock and data recovery module to said serial data input of said data serializer and clock generator module, bypassing said first and second digital portions.
19. The data communications device of claim 18 , wherein said data communications device forms part of a local communications node, and wherein said first and second SERDES devices are located on a common integrated circuit substrate at said local communications node.
20. A data communications device, comprising;
a first serializer-deserializer (SERDES) device including a first analog portion and a first digital portion, said first analog portion having a first serial port and a clock and data recovery module coupled to a receive portion of said first serial port, and said first digital portion coupled to an output of said clock and data recovery module;
a second SERDES device including a second analog portion and a second digital portion, said second analog portion having a second serial port and a data serializer and clock generator module coupled to a transmit portion of said second serial port, and said second digital portion coupled to an input of said data serializer and clock generator module;
a first signal path that connects said output of said clock and data recovery module to said input of said data serializer and clock generator module, bypassing said first and second digital portions; and
a second signal path that connects said first serial port to said second serial port, bypassing said clock and data recovery module and said data serializer and clock generator module.