Microprocessor in a security-sensitive system
View Patent ↗A Microprocessor ( 1 ) in a security-sensitive computing system for processing an operand according to an instruction is for improving its security provided with a modulo-based check hardware ( 2 ) to perform operations in parallel to the microprocessor ( 1 ) and for comparing both results regarding congruence.
1. A security-sensitive computing system, comprising:
a microprocessor configured to process at least one operand according to an instruction and output a microprocessor result; and
a modulo-based check hardware configured to perform operations in parallel to the microprocessor, wherein the check hardware is configured to:
perform at least one modulo operation on the at least one operand to generate a first modulo result,
perform at least one computation on the first modulo result based on the instruction to generate a first computation result,
perform at least one modulo operation on the first computation result to generate a second modulo result,
perform at least one modulo operation on the microprocessor result to generate a microprocessor modulo result, and
compare the second modulo result and the microprocessor modulo result to determine if they are congruent.
2. The computing system according to claim 1 , wherein the check hardware is built separately from the microprocessor in the same hierarchy.
3. The computing system according to claim 1 , wherein an error message is displayed if the second modulo result and the microprocessor modulo result are not congruent.
4. The computing system according to claim 1 , wherein the check hardware is configured to consider an overflow status signal.
5. The computing system according to claim 1 , wherein the at least one computation performed by the check hardware is at least one of addition, subtraction, multiplication, multiply and addition (MAD), and multiply and subtraction (MSUB).
6. The computing system according to claim 1 , wherein the check hardware is configured to receive the microprocessor result.
7. A security-sensitive computing system, comprising:
a microprocessor configured to process a first operand and a second operand according to an instruction and output a microprocessor result; and
a modulo-based check hardware configured to perform operations in parallel to the microprocessor, wherein the check hardware is configured to:
perform at least one modulo operation on the first operand to generate a first modulo result,
perform at least one modulo operation on the second operand to generate a second modulo result,
perform at least one computation on the first modulo result and the second modulo result based on the instruction to generate a first computation result,
perform at least one modulo operation on the first computation result to generate a third modulo result,
perform at least one modulo operation on the microprocessor result to generate a microprocessor modulo result, and
compare the third modulo result and the microprocessor modulo result to determine if they are congruent.
8. The computing system according to claim 7 , wherein the check hardware is built separately from the microprocessor in the same hierarchy.
9. The computing system according to claim 7 , wherein an error message is displayed if the second modulo result and the microprocessor modulo result are not congruent.
10. The computing system according to claim 7 , wherein the check hardware is configured to consider an overflow status signal.
11. The computing system according to claim 7 , wherein the at least one computation performed by the check hardware is at least one of addition, subtraction, multiplication, multiply and addition (MAD), and multiply and subtraction (MSUB).
12. A method for detecting an error in a security-sensitive computing system, comprising:
processing at least one operand in a microprocessor according to an instruction and outputting a microprocessor result;
generating a first modulo result in a check hardware by performing at least one modulo operation on the at least one operand;
generating first computation result in the check hardware by performing at least one computation on the first modulo result;
generating a second modulo result in the check hardware by performing at least one modulo operation on the first computation result;
generating a microprocessor modulo result in the check hardware by performing at least one modulo operation on the microprocessor result; and
comparing the second modulo result and the microprocessor modulo result in the check hardware to determine if they are congruent, wherein the check hardware operates in parallel to the microprocessor.
13. The method according to claim 12 , wherein the at least one computation is at least one of addition, subtraction, multiplication, multiply and addition (MAD), and multiply and subtraction (MSUB).