IP Library Granted Patent US 8,799,547
Granted Patent B2
US 8,799,547 · App. 12/668,409 · Granted Aug 5, 2014

Data packet processing method for a multi core processor

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Quick Facts
Patent No.
US 8,799,547
App. No.
12/668,409
Granted
Aug 5, 2014
Kind
B2
Abstract

A method for processing a data packet in a network server system comprising at least one central processor unit (CPU) having a plurality of cores; and a network interface for forming a connection to a network between the network and a designated CPU core, such that for all data packets received from the network an interrupt is created in the designated CPU core for received data packet processing. Each data packet received from the network is associated with an application connection established in a CPU core selected based on processor load and an interrupt thread is created on the CPU core associated with the application connection for processing the data packet. Each data packet being sent to the network is associated with an application connected established either in the CPU core in which the application is executing or an alternative CPU core selected based on processor load. Where the application connection is established in an alternative CPU core, an interrupt thread is created on the CPU core associated with the connection for processing the data packet.

Claims (47)

1. A method of processing a data packet comprising:

receiving an interrupt in a designated central processor unit (CPU) core within a multi core processor platform from a network interface for processing the data packet received from the network;

associating the data packet with an application connection established in a central processor unit (CPU) core selected based on processor load;

creating an interrupt thread on the CPU core associated with the application connection for processing the received data packet; and

selecting the CPU core in which to establish the application connection; and

establishing the application connection in the selected CPU core;

in which the steps of selecting a CPU core and establishing a connection are performed at session layer level of a network stack.

2. The method of claim 1 in which the CPU core is selected based on processor interrupt load for each CPU core.

3. The method of claim 2 in which the CPU core is selected giving preference to a CPU core sharing cache memory with a CPU core performing an operation related to the received packet.

4. The method of claim 2 in which the multi core processor is adapted to enable hyper-threading and in which a virtual CPU for establishing the application connection is selected in the CPU core selected giving preference to a non co-threaded CPU core.

5. The method of claim 2 in which the processor interrupt load is monitored by an operating system scheduling function.

6. The method of claim 1 further comprising the step of associating affinity for the application with the selected CPU core.

7. A method of processing a data packet comprising:

determining whether to process an outgoing data packet using a CPU core within a multi core processor platform executing an application or using an alternative central processor unit (CPU) core; and

where it is determined to use the alternative CPU core:

selecting the alternative CPU core for outgoing packet processing based on processor load;

establishing an application connection in the selected alternative CPU core;

associating the data packet with the application connection; and

creating an interrupt thread on the selected alternative CPU core for processing the data packet to the network interface;

in which the steps of selecting the alternative CPU core and establishing an application connection are performed at session layer level of a network stack.

8. The method of claim 7 in which the CPU core is selected based on processor interrupt load for each CPU core.

9. The method of claim 8 in which the CPU core is selected giving preference to a CPU core sharing cache memory with a CPU core performing an operation related to the data packet.

10. The method of claim 8 in which the multi core processor is adapted to enable hyper-threading and in which a virtual CPU for establishing the application connection is selected in the CPU core selected giving preference to a non co-threaded CPU core.

11. The method of claim 8 in which the processor interrupt load is monitored by an operating system scheduling function.

12. A network server system comprising:

at least one central processor unit (CPU) having a number of cores; and

a network interface for connecting to a network,

in which the network interface is adapted to create an interrupt in a designated CPU core for processing each data packet received from the network, and in which:

each data packet received from the network is associated with an application connection established in a selected CPU core at session layer level of a network stack;

the CPU core is selected based on processor load; and

an interrupt thread is created on the CPU core associated with the application connection for processing the data packet.

13. The network server system of claim 12 in which the CPU core is selected based on processor interrupt load for each CPU core.

14. The network server system of claim 13 in which the CPU core is selected giving preference to a CPU core sharing cache memory with a CPU core performing an operation related to the received packet.

15. The network server system of claim 13 in which the processor interrupt load for each CPU core is monitored by a operating system scheduler function.

16. The network server system of claim 13 in which the multi core processor is adapted to enable hyper-threading and in which a virtual CPU for establishing the application connection is selected in the CPU core selected giving preference to a non co-threaded CPU core.

17. The network server system of claim 12 in which, for data packets received from the network″ the processor is adapted to select a CPU core and establish the application connection at data link layer level of a network stack.

18. A network server system comprising:

a number of central processor units (CPU) each having a plurality of cores; and

a network interface configured to connect to a network and further configured to allow each CPU core to access the network, in which:

the network interface is adapted to create an interrupt in a designated CPU core for processing each data packet received from the network, and in which:

each data packet being sent to the network is associated with an application connection established either in the CPU core in which the application is executing, or an alternative CPU core selected based on processor load; and,

where the application connection is established in an alternative CPU core, an interrupt thread is created on the CPU core associated with the application connection for processing the data packet;

in which, for data packets being sent to the network, the processor is adapted to select a CPU core and establish the application connection at session layer level of a network stack.

19. The network server system of claim 18 in which the CPU core is selected based on processor interrupt load for each CPU core.

20. The network server system of claim 19 in which the CPU core is selected giving preference to a CPU core sharing cache memory with a CPU core performing an operation related to the received packet.

21. The network server system of claim 19 in which the processor interrupt load for each CPU core is monitored by a operating system scheduler function.

22. The network server system of claim 19 in which the multi core processor is adapted to enable hyper-threading and in which a virtual CPU for establishing the application connection is selected in a CPU core selected giving preference to a non co-threaded CPU core.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 24, 2021
From: OT PATENT ESCROW, LLC
To: VALTRUS INNOVATIONS LIMITED
Reel/Frame 055403/0001 →
PATENT ASSIGNMENT, SECURITY INTEREST, AND LIEN AGREEMENT Recorded Jan 26, 2021
From: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP; HEWLETT PACKARD ENTERPRISE COMPANY
To: OT PATENT ESCROW, LLC
Reel/Frame 055269/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE SECOND ASSIGNOR'S NAME FROM SHENOY ANANTH YLTHIMAR PREVIOUSLY RECORDED ON REEL 023766 FRAME 0213. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded May 9, 2020
From: MAHADEVAN, NILAKANTAN; SHENOY, ANANTH YELTHIMAR; LAKSHMINARAYAN, SRIKANTH
To: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Reel/Frame 052618/0935 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 12, 2010
From: MAHADEVAN, NILAKANTAN; SHENOY, ANANTH YLTHIMAR; LAKSHMINARAYAN, SRIKANTH
To: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Reel/Frame 023766/0213 →