Control sequencer
View Patent ↗An audio codec ( 100 ) is provided with a control sequencer ( 110 ) interposed between control interface logic ( 120 ) and control registers ( 130 ) of the codec. A memory ( 114, 116 ) associated with the control sequencer ( 110 ) enables a burst of operations to be preloaded into the audio codec. In response to a single command from an external control processor ( 20 ), the sequencer ( 110 ) can then execute the burst with precise delays between each operation and without further direction from the processor. This frees the processor ( 20 ) to concentrate on other tasks within the system, and/or to enter a low-power mode to conserve energy. The system may be a personal media player.
1. A codec comprising:
a control interface for receiving a control command from external to the codec,
memory for storing at least one sequence of stored commands, wherein each stored command comprises an operation and a delay time;
a plurality of control registers for controlling operation of the codec; and
a control sequencer responsive to said received control command to execute a specified said sequence of stored commands,
wherein said control sequencer is configured to perform the operation specified in a stored command to write control data to the control registers to control operation of the codec, and delay for a period of time based on said delay time of the stored command before performing the operation of the next stored command of the sequence.
2. The codec according to claim 1 further comprising control interface logic connected to the control interface, the control sequencer being interposed between the control interface logic and with the control registers.
3. The codec according to claim 2 further comprising a multiplexer operable to couple the control registers selectively to either the control sequencer or to the control interface logic.
4. The codec according to claim 2 wherein the control sequencer comprises a state machine for executing said at least one sequence of stored commands.
5. The codec according to claim 4 wherein said memory comprises a ROM for at least one predefined sequence of stored commands.
6. The codec according to claim 4 wherein the memory comprises a RAM for storing at least one sequence of stored commands input to the codec via the control interface logic.
7. The codec according to claim 2 further comprising a status register for storing a completion status of the sequence of stored commands executed by the sequencer.
8. The codec according to claim 7 wherein the status register is part of the control interface logic and is responsive to a signal sent from the control sequencer to the control interface logic.
9. The codec according to claim 1 further comprising a codec core arranged to receive one or more values stored in the control registers.
10. The codec according to claim 9 further comprising a data interface separate from said control interface, the data interface arranged to receive data and coupled to the codec core.
11. The codec according to claim 9 wherein the control interface is a combined control and data interface.
12. The codec according to claim 10 wherein the data is digital audio data, and further comprising an analogue audio interface for at least outputting an analogue audio signal.
13. The codec according to claim 1 wherein the sequence of stored commands is a power-up or power-down sequence for the codec.
14. The codec according to claim 12 wherein the sequence of stored commands is for producing a user interface sound via the analogue audio interface.
15. The codec according to claim 1 wherein the or each sequence of stored commands is variable in length so as to include differing numbers of operations.
16. The codec according to claim 1 wherein the delay time is defined by k2r where k is a constant and T is a delay coefficient.
17. The codec according to claim 1 wherein each of the control registers is arranged to store a word comprising a plurality of fields, and the control sequencer is arranged to carry out writes to individual said fields.
18. The codec according to claim 17 wherein each stored command includes fields for address, data, write enable and a mask which allows the write to be restricted to an individual field in the control registers.
19. A system comprising the codec according to claim 1 together with at least one processor arranged to supply at least said control command.
20. A system comprising the codec according to claim 10 together with a media and control processor arranged to supply said control command and said data.
21. The system according to claim 19 further comprising a plurality of functional blocks connected to said processor, said processor being arranged, following supply of said control command to the control sequencer, to supply a further command to a said functional block without waiting for execution of said sequence.
22. The system according to claim 21 , wherein the system is powered by a battery and the processor is arranged to enter a low-power or power-down state following supply of said control command, without waiting for execution of said sequence.
23. The system according to claim 21 , wherein the system is an audio apparatus.
24. The system according to claim 21 , wherein the system is a personal media player and the functional blocks include a display and a memory for storing media data.
25. The system according to claim 24 wherein the media player is for at least reproducing audio data among said media data.
26. A control sequencer for the codec of claim 1 .
27. A non-transitory storage medium including computer program code which, when implemented by a general-purpose logic circuit, provides the control sequencer of claim 26 .
28. A method of controlling a codec having one or more control registers and a control interface arranged to receive a control command from the outside, the method comprising:
receiving a control command via said control interface; and
triggering a control sequencer in response to said received command to execute a sequence of stored commands, said sequence being stored in a memory of the codec;
wherein each stored command comprises an operation and a delay time; and
wherein executing said sequence of stored commands comprises performing the operation specified in a stored command to write control data to the control registers to control operation of the codec, and delaying for a period of time based on said delay time of the stored command before performing the operation of the next stored command of the sequence.
29. The method according to claim 28 , further comprising multiplexing the control sequencer and the control interface logic to the control registers so as to couple the control registers selectively to either the control sequencer or to the control interface logic.
30. The method according to claim 28 , further comprising executing said sequence of stored commands using a state machine.
31. The method according to claim 30 , further comprising storing in a status register a completion status of the sequence of stored commands executed by the sequencer.
32. The method according to claim 28 , applied to a power-up or power-down sequence for the codec.