Method and circuit for DisplayPort video clock recovery
A method and a circuit are described for recovery of video clocks for a DisplayPort receiver. The disclosure includes two clock dividers, a direct digital synthesis (DDS), a fixed multiplier Phase-Locked Loop (PLL) on a DisplayPort video system. A DisplayPort receiver link clock is divided to a lower frequency as the input of the DDS which can lower the performance requirement on a DDS circuit. The output from a time stamp value indirectly controls a direct digital synthesis device, which then drives a PLL to generate the recovery clock signal. The technique is suitable for implementation on an integrated circuit and Field Programmable Gate array system.
1. A stream clock recovery device, comprising:
a receiver receiving a clock data along with its time stamped values;
the receiver further comprising:
a first clock divider to divide the clock frequency to a lower frequency;
a fixed multiplier phase locked loop (PLL) device for synthesizing an output clock;
a digital control logic circuit that converts the time stamped values into a reference clock and a divider factor;
a direct digital synthesis (DDS) device, wherein the DDS takes the frequency-divided signal from the first clock divider and the reference clock, and synthesizes an input signal for the PLL device; and
a second clock divider that applies the divider factor to the PLL output clock to create a recovered clock signal.
2. A stream clock recovery device of claim 1 , wherein the clock data is from a DisplayPort channel.
3. A stream clock recovery device of claim 1 , wherein the receiver is a DisplayPort receiver.
4. A stream clock recovery device of claim 1 , wherein the recovered clock is a DisplayPort recovered clock.