IP Library Granted Patent US 8,383,435
Granted Patent B2
US 8,383,435 · App. 12/685,802 · Granted Feb 26, 2013

Integrated photonic semiconductor devices and methods for making integrated photonic semiconductor devices

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Quick Facts
Patent No.
US 8,383,435
App. No.
12/685,802
Granted
Feb 26, 2013
Kind
B2
Abstract

A photonic semiconductor device and method are provided that ensure that the surface of the device upon completion of the SAG process is planar, or at least substantially planar, such that performance of the subsequent processes is facilitated, thereby enabling higher manufacturing yield to be achieved. A photonic semiconductor device and method are also provided that ensure that the isolation region of the device will have high resistance and low capacitance, without requiring the placement of a thick dielectric material beneath each of the contact pads. Eliminating the need to place thick dielectric materials underneath the contact pads eliminates the risk that the contact pads will peel away from the assembly.

Claims (9)

1. A method for performing a selective area growth (SAG) process when making a photonic semiconductor device that results in a substantially planar surface being formed at the completion of the SAG process, the method comprising:

providing a substrate having a lower surface and an upper surface;

forming a first layer structure on the upper surface of the substrate, the first layer structure having an upper surface and a lower surface, said first layer structure devoid of a multi quantum well (MQW) layer and devoid of a separate confinement heterostructure (SCH) layer, said first layer structure comprising:

a first layer of a first material disposed on the upper surface of the substrate, the first layer of material having an upper surface and a lower surface, the lower surface of said first layer of material corresponding to the lower surface of the first layer structure; and

a second layer of a second material disposed on the upper surface of the first layer of material, the second layer of material having an upper surface and a lower surface, the upper surface of said second layer of material corresponding to the upper surface of the first layer structure;

forming a mask pattern on the upper surface of said second layer of material such that at least one portion of said second layer of material is unmasked by the mask pattern and such that at least one portion of the second layer of material is masked by the mask pattern;

performing an etching process that etches away unmasked portions of the second layer of material to form at least one recess in the second layer of material, the at least one recess having a top corresponding to the upper surface of the second layer of material and a bottom opposite the top, the top of the at least one recess being wider than the bottom; and

performing a SAG process to form a second layer structure of the photonic semiconductor device, the second layer structure being formed in the at least one recess in the second layer of material, and the second layer structure comprising at least one MQW layer and at least one SCH layer, the second layer structure having a lower surface that is in contact with the upper surface of said first layer of the first layer structure, the upper surface of the second layer structure being substantially coplanar with the upper surface of the first layer structure.

2. The method of claim 1 , wherein the photonic semiconductor device being made by the method is a an electroabsorption modulator distributed feedback laser (EML) assembly, the EML device comprising an electroabsorption modulator (EAM) portion integrated and a distributed feedback laser (DFB) portion that are integrated together in the semiconductor device.

Assignments (7)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2020
From: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
To: BROADCOM INTERNATIONAL PTE. LTD.
Reel/Frame 053771/0901 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER TO 09/05/2018 PREVIOUSLY RECORDED AT REEL: 047230 FRAME: 0133. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047630/0456 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047230/0133 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032851-0001) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 037689/0001 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032851/0001 →