Transistor formation using capping layer
View Patent ↗A method of transistor formation using a capping layer in complimentary metal-oxide semiconductor (CMOS) structures is provided, the method including: depositing a conductive layer over an n-type field effect transistor (nFET) and over a p-type field effect transistor (pFET); depositing a capping layer directly over the conductive layer; etching the capping and conductive layers to form a capped gate conductor to gates of the nFET and pFET, respectively; ion-implanting the nFET transistor with a first dopant; and ion-implanting the pFET transistor with a second dopant, wherein ion-implanting a transistor substantially dopes its source and drain regions, but not its gate region.
1. A method of transistor formation using a capping layer in complimentary metal-oxide semiconductor (CMOS) structures, the method comprising:
depositing a conductive layer over an n-type field effect transistor (nFET) and over a p-type field effect transistor (pFET);
depositing a capping layer directly over the conductive layer;
etching the capping and conductive layers to form at least one capped gate conductor to gates of the nFET and pFET, respectively;
ion-implanting the nFET transistor with a first dopant;
ion-implanting the pFET transistor with a second dopant; and
remaining at least or capped gate conductor in the finished CMOS structure,
wherein ion-implanting at least one of the transistors substantially dopes its source and drain regions, but not its gate region.
2. A method as defined in claim 1 wherein the conductive layer comprises polycrystalline silicon.
3. A method as defined in claim 1 wherein the conductive layer comprises metal.
4. A method as defined in claim 1 wherein the capping layer comprises nitride.
5. A method as defined in claim 1 wherein the capping layer comprises oxide.
6. A method as defined in claim 1 wherein the first dopant comprises at least one of arsenic or phosphene.
7. A method as defined in claim 1 wherein the second dopant comprises boron di-fluoride.
8. A method as defined in claim 1 wherein ion-implanting the nFET and pFET substantially dopes the sources and drains of the transistors, but not the capped gates.
9. A method as defined in claim 1 wherein the gate conductor widths of the nFET and pFET are substantially the same.
10. A method of transistor formation using a capping layer in complimentary metal-oxide semiconductor (CMOS) structures, the method comprising:
depositing a conductive layer over an n-type field effect transistor (nFET) and over a p-type field effect transistor (pFET);
depositing a capping layer directly over the conductive layer;
etching the capping and conductive layers to form at least one capped gate conductor to gates of the nFET and pFET, respectively;
ion-implanting the nFET transistor with a first dopant;
ion-implanting the pFET transistor with a second dopant, wherein ion-implanting at least one of the transistors substantially dopes its source and drain regions, but not its gate region; and
substantially uncapping the pFET gate conductor, wherein ion-implanting the nFET substantially dopes the source and drain regions of the nFET, but not the capped gate region of the nFET, and ion-implanting the pFET substantially dopes the source and drain regions of the pFET as well as the substantially uncapped gate region of the pFET.
11. A method of transistor formation using a capping layer in complimentary metal-oxide (CMOS) structures, the method comprising:
depositing a conductive layer over an n-type field effect transistor (nFET) and over a p-type field effect transistor (pFET);
depositing a capping layer directly over the conductive layer;
etching the capping and conductive layers to form at least one capped gate conductor to gates of the nFET and pFET, respectively;
ion-implanting the nFET transistor with first dopant;
ion-implanting the pFET transistor with a second dopant, wherein ion-implanting at least one of the transistors substantially dopes its source and drain regions, but not its gate region; and
pre-doping at least one of the gate conductor or the gate region of at least one of the nFET or pFET.
12. A method as defined in claim 1 , further comprising removing the capping layer.
13. A method as defined in claim 1 , further comprising forming silicide on the nFET and pFET gate conductors.
14. A method as defined in claim 1 , further comprising forming at least one spacer on the gate conductors.
15. A method of transistor formation using a capping layer in complimentary metal-oxide semiconductor (CMOS) structures, the method comprising:
depositing a conductive layer over an n-type field effect transistor (nFET) and over a p-type field effect transistor (pFET);
depositing a capping layer directly over the conductive layer;
etching the capping and conductive layers to form at least one capped gate conductor to gates of the nFET and pFET, respectively;
ion-implanting the nFET transistor with, a first dopant;
ion-implanting the pFET transistor with a second dopant; and
forming at least one spacer on the gate conductors,
wherein ion-implanting at least of the transistors substantially dopes its source and drain regions, but not its gate region and wherein the at least one spacer comprises epitaxially grown silicon-germanium (eSiGe).
16. A method as defined in claim 14 wherein the at least one spacer comprises oxide.
17. A method as defined in claim 16 wherein the at least one oxide spacer comprises at least one of a re-oxidation layer, a low temperature oxidation (LTO) layer, or a plasma enhanced (PE) oxide layer.
18. A method as defined in claim 14 wherein the at least one spacer comprises a molecular layer deposition (MLD) nitride layer.
19. A method as defined in claim 14 , further comprising remaining the at least one spacer on the gate conductors in the finished CMOS structure.