Error-correcting apparatus including multiple error-correcting modules functioning in parallel and related method
View Patent ↗An apparatus for error-correcting an input signal to generate an output signal. The apparatus includes an unreliable-location determining module for determining unreliable-locations of the input signal and generating an indication signal accordingly, a first error-correcting module for error-correcting the input signal to generate a first candidate signal, a second error-correcting module coupled to the unreliable-location determining module for error-correcting the input signal with reference to the indication signal to generate a second candidate signal, and a selecting module coupled to the first and second error-correcting modules for selecting one of the first and second candidate signals to be the output signal.
1. An receiver for receiving concatenated codes over a network, the receiver comprising:
a first error-correcting module for error-correcting an input signal of the concatenated codes to generate a first candidate signal when the input signal found containing errors less than a threshold; and
a second error-correcting module, for error-correcting the input signal with reference to an indication signal for indicating unreliable-locations of the input signal of the concatenated codes to generate a second candidate signal when the input signal is found containing errors more than the threshold.
2. The receiver of claim 1 , wherein the input signal of the concatenated codes is a Reed-Solomon (RS) encoded signal.
3. The receiver of claim 1 , wherein the first error-correcting module comprises an error decoder, and the second error-correcting module comprises an error-erasure decoder.
4. The receiver of claim 1 , wherein the first and second error-correcting modules function in parallel.
5. The receiver of claim 1 , wherein the second error-correcting module error-corrects the input signal by regarding the unreliable-locations indicated by the indication signal as erasure locations.
6. The receiver of claim 1 , further comprising a selecting module, wherein the first error-correcting module further generates a first flag signal to indicate whether the input signal is successively error-corrected by the first error-correcting module to generate the first candidate signal, and the selecting module selects one of the first and second candidate signals to be the output signal according to the first flag signal.
7. The receiver of claim 6 , further comprising a selecting module, wherein if the first flag signal indicates that the input signal is successively error-corrected by the first error-correcting module to generate the first candidate signal, the selecting module selects the first candidate signal to be an output signal; and if the first flag signal indicates that the input signal is not successively error-corrected by the first error-correcting module to generate the first candidate signal, the selecting module further determines whether to select the second candidate signal to be the output signal.